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Remove idiv implementation
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There is no integer division in AVX
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sfegan committed Aug 7, 2024
1 parent 71cefa9 commit 8b4facc
Showing 1 changed file with 0 additions and 28 deletions.
28 changes: 0 additions & 28 deletions include/math/hex_array_vcl.hpp
Original file line number Diff line number Diff line change
Expand Up @@ -229,16 +229,6 @@ template<typename VCLArchitecture> class alignas(VCLArchitecture::vec_bytes) VCL
}
}

static inline void positive_hexid_to_ringid_segid_runid_idiv(
const int32_vt hexid, int32_vt& ringid, int32_vt& segid, int32_vt& runid)
{
ringid = positive_hexid_to_ringid(hexid);
const int32_vt ringid_minus_one = ringid - 1;
runid = hexid - ringid_to_nsites_contained(ringid_minus_one);
segid = runid/ringid;
runid -= segid*ringid;
}

static inline void hexid_to_ringid_segid_runid(
const int32_vt hexid, int32_vt& ringid, int32_vt& segid, int32_vt& runid)
{
Expand Down Expand Up @@ -1111,24 +1101,6 @@ inline void test_vcl_positive_hexid_to_ringid_segid_runid_muldiv(volatile unsign
}
}

inline void test_vcl_positive_hexid_to_ringid_segid_runid_idiv(volatile unsigned hexid,
unsigned& ringid, unsigned& segid, unsigned& runid, unsigned iterations = 1)
{
using Arch = calin::util::vcl::VCL256Architecture;
ringid = 0;
segid = 0;
runid = 0;
while(iterations--) {
Arch::int32_vt v_ringid;
Arch::int32_vt v_segid;
Arch::int32_vt v_runid;
VCL<Arch>::positive_hexid_to_ringid_segid_runid_idiv(hexid,v_ringid,v_segid,v_runid);
ringid += v_ringid[0];
segid += v_segid[0];
runid += v_runid[0];
}
}

#if 0
unsigned test_avx2_hexid_to_ringid(unsigned hexid);
unsigned test_avx2_ringid_to_nsites_contained(unsigned ringid);
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