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Merge pull request #28 from phip1611/x86
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serial also on arch x86
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phil-opp authored Jul 7, 2023
2 parents d401ea1 + 0c2d141 commit 85dde1c
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Showing 2 changed files with 5 additions and 5 deletions.
8 changes: 4 additions & 4 deletions src/lib.rs
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
//!
//!
//! ```no_run
//! # #[cfg(target_arch = "x86_64")]
//! # #[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
//! # fn main() {
//! use uart_16550::SerialPort;
//!
Expand All @@ -33,7 +33,7 @@
//! // To receive a byte:
//! let data = serial_port.receive();
//! # }
//! # #[cfg(not(target_arch = "x86_64"))]
//! # #[cfg(not(any(target_arch = "x86", target_arch = "x86_64")))]
//! # fn main() {}
//! ```
//!
Expand Down Expand Up @@ -74,12 +74,12 @@ macro_rules! wait_for {

/// Memory mapped implementation
mod mmio;
#[cfg(target_arch = "x86_64")]
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
/// Port asm commands implementation
mod port;

pub use crate::mmio::MmioSerialPort;
#[cfg(target_arch = "x86_64")]
#[cfg(any(target_arch = "x86", target_arch = "x86_64"))]
pub use crate::port::SerialPort;

bitflags! {
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2 changes: 1 addition & 1 deletion src/port.rs
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@ use x86_64::instructions::port::{Port, PortReadOnly, PortWriteOnly};
use crate::LineStsFlags;

/// A port-mapped UART.
#[cfg_attr(docsrs, doc(cfg(target_arch = "x86_64")))]
#[cfg_attr(docsrs, doc(cfg(any(target_arch = "x86", target_arch = "x86_64"))))]
pub struct SerialPort {
data: Port<u8>,
int_en: PortWriteOnly<u8>,
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