Rollup of 13 pull requests

Cargo.lock

@@ -1848,9 +1848,9 @@ dependencies = [
 
 [[package]]
 name = "mdbook"
-version = "0.4.2"
+version = "0.4.3"
 source = "registry+https://github.com/rust-lang/crates.io-index"
-checksum = "b75e31ae4eaa0e45e17ee2b6b9e3ed969c3c6ff12bb4c2e352c42493f4ebb706"
+checksum = "29be448fcafb00c5a8966c4020c2a5ffbbc333e5b96d0bb5ef54b5bd0524d9ff"
 dependencies = [
  "ammonia",
  "anyhow",

compiler/rustc_builtin_macros/src/format.rs

@@ -543,9 +543,12 @@ impl<'a, 'b> Context<'a, 'b> {
                             let idx = self.args.len();
                             self.arg_types.push(Vec::new());
                             self.arg_unique_types.push(Vec::new());
-                            self.args.push(
-                                self.ecx.expr_ident(self.fmtsp, Ident::new(name, self.fmtsp)),
-                            );
+                            let span = if self.is_literal {
+                                *self.arg_spans.get(self.curpiece).unwrap_or(&self.fmtsp)
+                            } else {
+                                self.fmtsp
+                            };
+                            self.args.push(self.ecx.expr_ident(span, Ident::new(name, span)));
                             self.names.insert(name, idx);
                             self.verify_arg_type(Exact(idx), ty)
                         } else {

compiler/rustc_codegen_llvm/src/asm.rs

@@ -259,6 +259,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
                 InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
                 InlineAsmArch::Nvptx64 => {}
                 InlineAsmArch::Hexagon => {}
+                InlineAsmArch::Mips => {}
             }
         }
         if !options.contains(InlineAsmOptions::NOMEM) {
@@ -505,6 +506,8 @@ fn reg_to_llvm(reg: InlineAsmRegOrRegClass, layout: Option<&TyAndLayout<'tcx>>)
             InlineAsmRegClass::Arm(ArmInlineAsmRegClass::dreg)
             | InlineAsmRegClass::Arm(ArmInlineAsmRegClass::qreg) => "w",
             InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => "r",
+            InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => "r",
+            InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => "f",
             InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => "h",
             InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => "r",
             InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => "l",
@@ -551,6 +554,7 @@ fn modifier_to_llvm(
             }
         }
         InlineAsmRegClass::Hexagon(_) => None,
+        InlineAsmRegClass::Mips(_) => None,
         InlineAsmRegClass::Nvptx(_) => None,
         InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::reg)
         | InlineAsmRegClass::RiscV(RiscVInlineAsmRegClass::freg) => None,
@@ -603,6 +607,8 @@ fn dummy_output_type(cx: &CodegenCx<'ll, 'tcx>, reg: InlineAsmRegClass) -> &'ll
             cx.type_vector(cx.type_i64(), 2)
         }
         InlineAsmRegClass::Hexagon(HexagonInlineAsmRegClass::reg) => cx.type_i32(),
+        InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg) => cx.type_i32(),
+        InlineAsmRegClass::Mips(MipsInlineAsmRegClass::freg) => cx.type_f32(),
         InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg16) => cx.type_i16(),
         InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg32) => cx.type_i32(),
         InlineAsmRegClass::Nvptx(NvptxInlineAsmRegClass::reg64) => cx.type_i64(),
@@ -700,6 +706,12 @@ fn llvm_fixup_input(
                 value
             }
         }
+        (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
+            // MIPS only supports register-length arithmetics.
+            Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
+            Primitive::F32 => bx.bitcast(value, bx.cx.type_i32()),
+            _ => value,
+        },
         _ => value,
     }
 }
@@ -768,6 +780,13 @@ fn llvm_fixup_output(
                 value
             }
         }
+        (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
+            // MIPS only supports register-length arithmetics.
+            Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
+            Primitive::Int(Integer::I16, _) => bx.trunc(value, bx.cx.type_i16()),
+            Primitive::F32 => bx.bitcast(value, bx.cx.type_f32()),
+            _ => value,
+        },
         _ => value,
     }
 }
@@ -831,6 +850,12 @@ fn llvm_fixup_output_type(
                 layout.llvm_type(cx)
             }
         }
+        (InlineAsmRegClass::Mips(MipsInlineAsmRegClass::reg), Abi::Scalar(s)) => match s.value {
+            // MIPS only supports register-length arithmetics.
+            Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
+            Primitive::F32 => cx.type_i32(),
+            _ => layout.llvm_type(cx),
+        },
         _ => layout.llvm_type(cx),
     }
 }

compiler/rustc_codegen_llvm/src/builder.rs

@@ -21,7 +21,6 @@ use rustc_target::abi::{self, Align, Size};
 use rustc_target::spec::{HasTargetSpec, Target};
 use std::borrow::Cow;
 use std::ffi::CStr;
-use std::iter::TrustedLen;
 use std::ops::{Deref, Range};
 use std::ptr;
 use tracing::debug;
@@ -179,7 +178,7 @@ impl BuilderMethods<'a, 'tcx> for Builder<'a, 'll, 'tcx> {
         &mut self,
         v: &'ll Value,
         else_llbb: &'ll BasicBlock,
-        cases: impl ExactSizeIterator<Item = (u128, &'ll BasicBlock)> + TrustedLen,
+        cases: impl ExactSizeIterator<Item = (u128, &'ll BasicBlock)>,
     ) {
         let switch =
             unsafe { llvm::LLVMBuildSwitch(self.llbuilder, v, else_llbb, cases.len() as c_uint) };

compiler/rustc_codegen_llvm/src/lib.rs

@@ -12,7 +12,6 @@
 #![feature(in_band_lifetimes)]
 #![feature(nll)]
 #![feature(or_patterns)]
-#![feature(trusted_len)]
 #![recursion_limit = "256"]
 
 use back::write::{create_informational_target_machine, create_target_machine};

compiler/rustc_codegen_ssa/src/lib.rs

@@ -6,7 +6,6 @@
 #![feature(in_band_lifetimes)]
 #![feature(nll)]
 #![feature(or_patterns)]
-#![feature(trusted_len)]
 #![feature(associated_type_bounds)]
 #![recursion_limit = "256"]
 

compiler/rustc_codegen_ssa/src/traits/builder.rs

@@ -18,7 +18,6 @@ use rustc_middle::ty::Ty;
 use rustc_target::abi::{Abi, Align, Scalar, Size};
 use rustc_target::spec::HasTargetSpec;
 
-use std::iter::TrustedLen;
 use std::ops::Range;
 
 #[derive(Copy, Clone)]
@@ -60,7 +59,7 @@ pub trait BuilderMethods<'a, 'tcx>:
         &mut self,
         v: Self::Value,
         else_llbb: Self::BasicBlock,
-        cases: impl ExactSizeIterator<Item = (u128, Self::BasicBlock)> + TrustedLen,
+        cases: impl ExactSizeIterator<Item = (u128, Self::BasicBlock)>,
     );
     fn invoke(
         &mut self,

compiler/rustc_feature/src/active.rs

@@ -584,6 +584,9 @@ declare_features! (
     /// Allows non trivial generic constants which have to be manually propageted upwards.
     (active, const_evaluatable_checked, "1.48.0", Some(76560), None),
 
+    /// Allows basic arithmetic on floating point types in a `const fn`.
+    (active, const_fn_floating_point_arithmetic, "1.48.0", Some(57241), None),
+
     // -------------------------------------------------------------------------
     // feature-group-end: actual feature gates
     // -------------------------------------------------------------------------

compiler/rustc_middle/src/ty/mod.rs

@@ -2675,7 +2675,7 @@ impl<'tcx> ClosureKind {
         }
     }
 
-    /// Returns `true` if this a type that impls this closure kind
+    /// Returns `true` if a type that impls this closure kind
     /// must also implement `other`.
     pub fn extends(self, other: ty::ClosureKind) -> bool {
         match (self, other) {

compiler/rustc_mir/src/transform/check_consts/ops.rs

@@ -112,6 +112,30 @@ impl NonConstOp for Abort {
     }
 }
 
+#[derive(Debug)]
+pub struct FloatingPointOp;
+impl NonConstOp for FloatingPointOp {
+    const STOPS_CONST_CHECKING: bool = true;
+
+    fn status_in_item(&self, ccx: &ConstCx<'_, '_>) -> Status {
+        if ccx.const_kind() == hir::ConstContext::ConstFn {
+            Status::Unstable(sym::const_fn_floating_point_arithmetic)
+        } else {
+            Status::Allowed
+        }
+    }
+
+    fn emit_error(&self, ccx: &ConstCx<'_, '_>, span: Span) {
+        feature_err(
+            &ccx.tcx.sess.parse_sess,
+            sym::const_fn_floating_point_arithmetic,
+            span,
+            &format!("floating point arithmetic is not allowed in {}s", ccx.const_kind()),
+        )
+        .emit();
+    }
+}
+
 #[derive(Debug)]
 pub struct NonPrimitiveOp;
 impl NonConstOp for NonPrimitiveOp {

compiler/rustc_mir/src/transform/check_consts/validation.rs

@@ -540,8 +540,12 @@ impl Visitor<'tcx> for Validator<'mir, 'tcx> {
 
             Rvalue::UnaryOp(_, ref operand) => {
                 let ty = operand.ty(self.body, self.tcx);
-                if !(ty.is_integral() || ty.is_bool()) {
-                    self.check_op(ops::NonPrimitiveOp)
+                if is_int_bool_or_char(ty) {
+                    // Int, bool, and char operations are fine.
+                } else if ty.is_floating_point() {
+                    self.check_op(ops::FloatingPointOp);
+                } else {
+                    span_bug!(self.span, "non-primitive type in `Rvalue::UnaryOp`: {:?}", ty);
                 }
             }
 
@@ -550,7 +554,9 @@ impl Visitor<'tcx> for Validator<'mir, 'tcx> {
                 let lhs_ty = lhs.ty(self.body, self.tcx);
                 let rhs_ty = rhs.ty(self.body, self.tcx);
 
-                if let ty::RawPtr(_) | ty::FnPtr(..) = lhs_ty.kind() {
+                if is_int_bool_or_char(lhs_ty) && is_int_bool_or_char(rhs_ty) {
+                    // Int, bool, and char operations are fine.
+                } else if lhs_ty.is_fn_ptr() || lhs_ty.is_unsafe_ptr() {
                     assert_eq!(lhs_ty, rhs_ty);
                     assert!(
                         op == BinOp::Eq
@@ -563,12 +569,15 @@ impl Visitor<'tcx> for Validator<'mir, 'tcx> {
                     );
 
                     self.check_op(ops::RawPtrComparison);
-                }
-
-                if !(lhs_ty.is_integral() || lhs_ty.is_bool() || lhs_ty.is_char())
-                    || !(rhs_ty.is_integral() || rhs_ty.is_bool() || rhs_ty.is_char())
-                {
-                    self.check_op(ops::NonPrimitiveOp)
+                } else if lhs_ty.is_floating_point() || rhs_ty.is_floating_point() {
+                    self.check_op(ops::FloatingPointOp);
+                } else {
+                    span_bug!(
+                        self.span,
+                        "non-primitive type in `Rvalue::BinaryOp`: {:?} ⚬ {:?}",
+                        lhs_ty,
+                        rhs_ty
+                    );
                 }
             }
         }
@@ -867,3 +876,7 @@ fn place_as_reborrow(
         }
     })
 }
+
+fn is_int_bool_or_char(ty: Ty<'_>) -> bool {
+    ty.is_bool() || ty.is_integral() || ty.is_char()
+}

compiler/rustc_span/src/symbol.rs

@@ -351,6 +351,7 @@ symbols! {
         const_evaluatable_checked,
         const_extern_fn,
         const_fn,
+        const_fn_floating_point_arithmetic,
         const_fn_transmute,
         const_fn_union,
         const_generics,

compiler/rustc_target/src/asm/mips.rs

@@ -0,0 +1,132 @@
+use super::{InlineAsmArch, InlineAsmType};
+use rustc_macros::HashStable_Generic;
+use std::fmt;
+
+def_reg_class! {
+    Mips MipsInlineAsmRegClass {
+        reg,
+        freg,
+    }
+}
+
+impl MipsInlineAsmRegClass {
+    pub fn valid_modifiers(self, _arch: super::InlineAsmArch) -> &'static [char] {
+        &[]
+    }
+
+    pub fn suggest_class(self, _arch: InlineAsmArch, _ty: InlineAsmType) -> Option<Self> {
+        None
+    }
+
+    pub fn suggest_modifier(
+        self,
+        _arch: InlineAsmArch,
+        _ty: InlineAsmType,
+    ) -> Option<(char, &'static str)> {
+        None
+    }
+
+    pub fn default_modifier(self, _arch: InlineAsmArch) -> Option<(char, &'static str)> {
+        None
+    }
+
+    pub fn supported_types(
+        self,
+        _arch: InlineAsmArch,
+    ) -> &'static [(InlineAsmType, Option<&'static str>)] {
+        match self {
+            Self::reg => types! { _: I8, I16, I32, F32; },
+            Self::freg => types! { _: F32; },
+        }
+    }
+}
+
+// The reserved registers are somewhat taken from <https://git.io/JUR1k#L150>.
+def_regs! {
+    Mips MipsInlineAsmReg MipsInlineAsmRegClass {
+        v0: reg = ["$2", "$v0"],
+        v1: reg = ["$3", "$v1"],
+        a0: reg = ["$4", "$a0"],
+        a1: reg = ["$5", "$a1"],
+        a2: reg = ["$6", "$a2"],
+        a3: reg = ["$7", "$a3"],
+        // FIXME: Reserve $t0, $t1 if in mips16 mode.
+        t0: reg = ["$8", "$t0"],
+        t1: reg = ["$9", "$t1"],
+        t2: reg = ["$10", "$t2"],
+        t3: reg = ["$11", "$t3"],
+        t4: reg = ["$12", "$t4"],
+        t5: reg = ["$13", "$t5"],
+        t6: reg = ["$14", "$t6"],
+        t7: reg = ["$15", "$t7"],
+        s0: reg = ["$16", "$s0"],
+        s1: reg = ["$17", "$s1"],
+        s2: reg = ["$18", "$s2"],
+        s3: reg = ["$19", "$s3"],
+        s4: reg = ["$20", "$s4"],
+        s5: reg = ["$21", "$s5"],
+        s6: reg = ["$22", "$s6"],
+        s7: reg = ["$23", "$s7"],
+        t8: reg = ["$24", "$t8"],
+        t9: reg = ["$25", "$t9"],
+        f0: freg = ["$f0"],
+        f1: freg = ["$f1"],
+        f2: freg = ["$f2"],
+        f3: freg = ["$f3"],
+        f4: freg = ["$f4"],
+        f5: freg = ["$f5"],
+        f6: freg = ["$f6"],
+        f7: freg = ["$f7"],
+        f8: freg = ["$f8"],
+        f9: freg = ["$f9"],
+        f10: freg = ["$f10"],
+        f11: freg = ["$f11"],
+        f12: freg = ["$f12"],
+        f13: freg = ["$f13"],
+        f14: freg = ["$f14"],
+        f15: freg = ["$f15"],
+        f16: freg = ["$f16"],
+        f17: freg = ["$f17"],
+        f18: freg = ["$f18"],
+        f19: freg = ["$f19"],
+        f20: freg = ["$f20"],
+        f21: freg = ["$f21"],
+        f22: freg = ["$f22"],
+        f23: freg = ["$f23"],
+        f24: freg = ["$f24"],
+        f25: freg = ["$f25"],
+        f26: freg = ["$f26"],
+        f27: freg = ["$f27"],
+        f28: freg = ["$f28"],
+        f29: freg = ["$f29"],
+        f30: freg = ["$f30"],
+        f31: freg = ["$f31"],
+        #error = ["$0", "$zero"] =>
+            "constant zero cannot be used as an operand for inline asm",
+        #error = ["$1", "$at"] =>
+            "reserved for assembler (Assembler Temp)",
+        #error = ["$26", "$k0"] =>
+            "OS-reserved register cannot be used as an operand for inline asm",
+        #error = ["$27", "$k1"] =>
+            "OS-reserved register cannot be used as an operand for inline asm",
+        #error = ["$28", "$gp"] =>
+            "the global pointer cannot be used as an operand for inline asm",
+        #error = ["$29", "$sp"] =>
+            "the stack pointer cannot be used as an operand for inline asm",
+        #error = ["$30", "$s8", "$fp"] =>
+            "the frame pointer cannot be used as an operand for inline asm",
+        #error = ["$31", "$ra"] =>
+            "the return address register cannot be used as an operand for inline asm",
+    }
+}
+
+impl MipsInlineAsmReg {
+    pub fn emit(
+        self,
+        out: &mut dyn fmt::Write,
+        _arch: InlineAsmArch,
+        _modifier: Option<char>,
+    ) -> fmt::Result {
+        out.write_str(self.name())
+    }
+}