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Refactor ty::FnSig to contain a &'tcx Slice<Ty<'tcx>> #38097
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variadic: a.variadic}) | ||
let inputs_and_output = a.inputs().into_iter().cloned() | ||
.zip(b.inputs().into_iter().cloned()) | ||
.zip(iter::repeat(false)) |
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This can be done with .map
.
.map(|i| i.fold_with(folder)) | ||
.collect::<AccumulateVec<[_; 8]>>(); | ||
ty::FnSig { | ||
inputs_and_output: folder.tcx().intern_type_list(&inputs_and_output), |
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I think you can just fold the list wholesale.
pub type PolyFnSig<'tcx> = Binder<FnSig<'tcx>>; | ||
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impl<'tcx> PolyFnSig<'tcx> { | ||
pub fn inputs(&self) -> ty::Binder<Vec<Ty<'tcx>>> { | ||
self.map_bound_ref(|fn_sig| fn_sig.inputs.clone()) | ||
pub fn inputs<'a>(&'a self) -> Binder<&[Ty<'tcx>]> { |
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The elision abuse here looks odd.
@@ -1243,10 +1252,6 @@ impl<'a, 'gcx, 'tcx> TyS<'tcx> { | |||
} | |||
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// Type accessors for substructures of types | |||
pub fn fn_args(&self) -> ty::Binder<Vec<Ty<'tcx>>> { | |||
self.fn_sig().inputs() |
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You could keep this returning a slice.
}; | ||
let tuple_input_ty = tcx.intern_tup(sig.inputs()); | ||
let sig = tcx.mk_fn_sig( | ||
iter::once(bare_fn_ty_maybe_ref).chain(iter::once(tuple_input_ty)), |
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You're using iter::once
a bit too much - try arrays instead.
..sig | ||
}); | ||
let sig = sig.map_bound(|sig| tcx.mk_fn_sig( | ||
iter::once(env_ty).chain(sig.inputs().into_iter().cloned()), |
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Could you avoid .into_iter()
on slices? It's just .iter()
.
@@ -1595,7 +1595,8 @@ impl<'o, 'gcx: 'tcx, 'tcx> AstConv<'gcx, 'tcx>+'o { | |||
// checking for here would be considered early bound | |||
// anyway.) | |||
let inputs = bare_fn_ty.sig.inputs(); | |||
let late_bound_in_args = tcx.collect_constrained_late_bound_regions(&inputs); | |||
let late_bound_in_args = tcx.collect_constrained_late_bound_regions( | |||
&inputs.map_bound(|i| i.to_owned())); |
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Why would this be needed? Looks like a bug?
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TypeFoldable
isn't implemented for &[Ty<'tcx>]
, which is what we have, so we need to cast it to a vector in order to pass it here. This is rather unfortunate, but I'm not sure how much we can do. It may be worth pointing out that the use is a visit_with on it, so it's possible this can be refactored into passing either the slice or an iterator to solve this problem. I can look into that if you'd like.
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What is purpose of this? |
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I believe there are a couple of purposes:
@eddyb may be able to suggest other reasons. @eddyb Ready for another review pass. |
☔ The latest upstream changes (presumably #38053) made this pull request unmergeable. Please resolve the merge conflicts. |
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Rebased. |
}), | ||
sig: ty::Binder(tcx.mk_fn_sig( | ||
iter::once(tcx.types.isize) | ||
.chain(iter::once(tcx.mk_imm_ptr(tcx.mk_imm_ptr(tcx.types.u8)))), |
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Could you use slice iterators, here and elsewhere?
@Mark-Simulacrum Can you move the contents of that comment into the description? You may also want to mention that the drop glue thing is about arenas, both in terms of cost of dropping/reusing the temporary ones currently and experiments with unified arenas in the future. |
@rust-lang/compiler Any objections? This is ready to land otherwise, modulo a few "style" tweaks. |
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Fixed style nit (I couldn't find any other places I chained iter::once together). Added the comment for reasons why we want this to the description. |
☔ The latest upstream changes (presumably #38121) made this pull request unmergeable. Please resolve the merge conflicts. |
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Rebased. |
@bors r+ |
📌 Commit 296ec5f has been approved by |
Refactor ty::FnSig to contain a &'tcx Slice<Ty<'tcx>> We refactor this in order to achieve the following wins: - Decrease the size of `FnSig` (`Vec` + `bool`: 32, `&Slice` + `bool`: 24). - Potentially decrease total allocated memory due to arena-allocating `FnSig` inputs/output; since they are allocated in the type list arena, other users of type lists can reuse the same allocation for an equivalent type list. - Remove the last part of the type system which needs drop glue (#37965 removed the other remaining part). This makes arenas containing `FnSig` faster to drop (since we don't need to drop a Vec for each one), and makes reusing them without clearing/dropping potentially possible. r? @eddyb
Nice! |
We refactor this in order to achieve the following wins:
FnSig
(Vec
+bool
: 32,&Slice
+bool
: 24).FnSig
inputs/output; since they are allocated in the type list arena, other users of type lists can reuse the same allocation for an equivalent type list.FnSig
faster to drop (since we don't need to drop a Vec for each one), and makes reusing them without clearing/dropping potentially possible.r? @eddyb