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Cherry-pick improvements for AVR codegen #149

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Closed

Cherry-pick improvements for AVR codegen #149

wants to merge 23 commits into from

Commits on Jul 23, 2023

  1. [AVR] Fix incorrect decoding of conditional branch instructions 

    This patch fixes the inaccurate decoding of the offset operand of
the conditional branch instructions.

Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D140816
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  2. [AVR][NFC] Remove redundant target feature PROGMEM 

    The functionality of FeaturePROGMEM is all equivalant to FeatureLPM.

Reviewed By: Chenbing.Zheng, aykevl

Differential Revision: https://reviews.llvm.org/D141242
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  3. [AVR][NFC] Refactor 'AVRAsmPrinter::PrintAsmOperand' 

    Reviewed By: Chenbing.Zheng, aykevl

Differential Revision: https://reviews.llvm.org/D142170
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  4. [AVR] Optimize 16-bit comparison with a constant 

    Fixes llvm#30923

Reviewed By: jacquesguan, aykevl

Differential Revision: https://reviews.llvm.org/D142281
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  5. [AVR] Fix inaccurate offsets in PC relative branch instructions 

    In avr-gcc, the destination of "rjmp label + offset" is address
'label + offset', while destination of "rjmp . + offset" is
'address_of_rjmp + offset + 2'.

Clang is in accordance with avr-gcc for "rjmp label + offset", but
emits incorrect destination of "rjmp . + offset" to
'address_of_rjmp + offset', in which the expected offset 2 is missing.

This patch fixes the above issue.

Fixes llvm#60019

Reviewed By: jacquesguan, aykevl

Differential Revision: https://reviews.llvm.org/D143901
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  6. [AVR][MC] Add ELF flag 'EF_AVR_LINKRELAX_PREPARED' to OBJ files 

    This is in accordance with avr-gcc, even '-mno-relax' is specified
to avr-gcc, this flag will also be added to the output relocatables.

With this flag set, the GNU ld will perform long call -> short call
optimization for AVR, otherwise not.

Fixes llvm#54508

Reviewed By: MaskRay, jacquesguan, aykevl

Differential Revision: https://reviews.llvm.org/D144617
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  7. [AVR] Fix incorrect flags of livein registers when spilling them 

    In AVRFrameLowering::spillCalleeSavedRegisters(), when a 16-bit
livein register is spilled, two PUSH instructions are generated
for the higher and lower 8-bit registers. But these two 8-bit
registers are marked as killed in the two PUSH instructions, so
any future use of them will cause a crash.

This patch fixes the above issue by adding the two sub 8-bit
registers to the livein list.

Fixes llvm#56423

Reviewed By: jacquesguan

Differential Revision: https://reviews.llvm.org/D144720
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  8. [AVR] Fix incorrect expansion of the pseudo 'ELPMBRdZ' instruction 

    The 'ELPM' instruction has three forms:

--------------------------
| form        | feature  |
| ----------- | -------- |
| ELPM        | hasELPM  |
| ELPM Rd, Z  | hasELPMX |
| ELPM Rd, Z+ | hasELPMX |
--------------------------

The second form is always used in the expansion of the pseudo
instruction 'ELPMBRdZ'. But for devices without ELPMX but only
with ELPM, only the first form can be emitted.

Reviewed By: jacquesguan

Differential Revision: https://reviews.llvm.org/D141221
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  9. [AVR] Do not emit 'LPM Rd, Z' on devices without FeatureLPMX 

    The 'LPM' instruction has three forms:

------------------------
| form       | feature |
| ---------- | --------|
| LPM        | hasLPM  |
| LPM Rd, Z  | hasLPMX |
| LPM Rd, Z+ | hasLPMX |
------------------------

The second form is always selected in ISelDAGToDAG, even on devices
without FeatureLPMX. This patch emits "LPM + MOV" on devices with
only FeatureLPM.

Reviewed By: jacquesguan

Differential Revision: https://reviews.llvm.org/D141246
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  10. [AVR] Fix incorrect expansion of pseudo instructions LPMWRdZ/ELPMWRdZ 

    The 'ELPM' instruction has three forms:

--------------------------
| form        | feature  |
| ----------- | -------- |
| ELPM        | hasELPM  |
| ELPM Rd, Z  | hasELPMX |
| ELPM Rd, Z+ | hasELPMX |
--------------------------

The second form is always used in the expansion of pseudo instructions
LPMWRdZ/ELPMWRdZ. But for devices without ELPMX and with only ELPM,
only the first form can be used.

Reviewed By: aykevl, Miss_Grape

Differential Revision: https://reviews.llvm.org/D141264
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  11. [AVR] Reject invalid LDD instruction with explicit error 

    We should reject "ldd Rn, X" with explicit error message
rather than "llvm_unreachable" in llvm's release build.

Fixes llvm#62012

Reviewed By: Miss_Grape

Differential Revision: https://reviews.llvm.org/D147877
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  12. [AVR][NFC] Fix errors in commit 6e57f68

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  13. [AVR] Disable post increment load from program memory space 

    We temporarily only allow post increment load/store from/to data memory,
and disable post increment load from program space.

Updates llvm#59914

Reviewed By: mzh

Differential Revision: https://reviews.llvm.org/D147761
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  14. [AVR] Fix an issue of writing 16-bit ports 

    For 16-bit ports, the normal devices reqiure writing high byte first
and then low byte. But the XMEGA devices require the reverse order.

Fixes llvm#58395

Reviewed By: aykevl, jacquesguan

Differential Revision: https://reviews.llvm.org/D141752
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  15. [AVR] Fix incorrect operands of pseudo instruction 'ROLBRd' 

    Fixes llvm#63098

Reviewed by: benshi001

Differential Revision: https://reviews.llvm.org/D152063
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  16. [AVR][NFC][test] Suppement a test of the pseudo instruction RORBRd 

    Reviewed By: aykevl, Patryk27

Differential Revision: https://reviews.llvm.org/D152087
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  17. [AVR][NFC][test] Supplement more tests of 8-bit rotation 

    Reviewed By: Patryk27, jacquesguan

Differential Revision: https://reviews.llvm.org/D152129
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  18. [AVR][NFC] Improve CodeGen tests 

    Reviewed By: Patryk27

Differential Revision: https://reviews.llvm.org/D152605
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  19. [AVR] Enable sub register liveness 

    Reviewed By: Patryk27

Differential Revision: https://reviews.llvm.org/D152606
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  20. [AVR] Fix incorrect expansion of pseudo instruction ROLBRd 

    Since ROLBRd needs an implicit R1 (on AVR) or an implicit R17 (on AVRTiny),
we split ROLBRd to ROLBRdR1 (on AVR) and ROLBRdR17 (on AVRTiny).

Reviewed By: aykevl, Patryk27

Differential Revision: https://reviews.llvm.org/D152248
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  21. [AVR] Optimize 8-bit rotation when rotation bits >= 4 

    Fixes llvm#63100

Reviewed By: aykevl, Patryk27, jacquesguan

Differential Revision: https://reviews.llvm.org/D152130
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  22. [AVR] Optimize 8-bit rotation when rotation bits == 3 

    Fixes llvm#63100

Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D152365
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  23. [AVR] Expand shifts of all types except int8 and int16 

    Currently our AVRShiftExpand pass expands only 32-bit shifts, with the
assumption that other kinds of shifts (e.g. 64-bit ones) are
automatically reduced to 8-bit ones by LLVM during ISel.

However this is not always true and causes problems in the rust-lang runtime.

This commit changes the logic a bit, so that instead of expanding only
32-bit shifts, we expand shifts of all types except 8-bit and 16-bit.

This is not the most optimal solution, because 64-bit shifts can be
expanded to 32-bit shifts which has been deeply optimized.

I've checked the generated code using rustc + simavr, and all shifts
seem to behave correctly.

Spotted in the wild in rustc:
rust-lang/compiler-builtins#523
rust-lang/rust#112140

Reviewed By: benshi001

Differential Revision: https://reviews.llvm.org/D154785
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