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According to the Arm Architecture Reference Manual (DDI 0487H.a), sections C5.2.5 and C5.2.6,
ESR_EL1
andESR_EL2
can be written to. Whether the write succeeds depends on which exception level we are running in, but this is not a concern for the aarch64-cpu crate.Implement the Writeable interface for
ESR_EL1
andESR_EL2
.