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| Original file line number | Diff line number | Diff line change |
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| `timescale 1ns / 1ps | ||
| ////////////////////////////////////////////////////////////////////////////////// | ||
| // Company: | ||
| // Engineer: | ||
| // | ||
| // Create Date: 12/06/2023 03:56:06 PM | ||
| // Design Name: | ||
| // Module Name: acc_top | ||
| // Project Name: | ||
| // Target Devices: | ||
| // Tool Versions: | ||
| // Description: | ||
| // | ||
| // Dependencies: | ||
| // | ||
| // Revision: | ||
| // Revision 0.01 - File Created | ||
| // Additional Comments: | ||
| // | ||
| ////////////////////////////////////////////////////////////////////////////////// | ||
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| module bf16_accelerator_top( | ||
| input logic clk, | ||
| input logic reset, | ||
| input logic enable, // Enable signal for the accelerator | ||
| input logic [31:0] operand_a, // First operand | ||
| input logic [15:0] operand_b, // Second operand | ||
| input logic [31:0] operand_c, // Third operand for FMA operations | ||
| input logic [3:0] operation, // Operation type | ||
| output logic [31:0] result, // Result of the operation | ||
| output logic [3:0] fpcsr, // Floating-point control and status register | ||
| output logic valid // Output valid signal | ||
| ); | ||
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| // Internal enable signals for submodules | ||
| logic conv_enable, maxmin_enable, addmul_enable; | ||
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| // Internal result and FPCSR signals from submodules | ||
| logic [15:0] maxmin_result; | ||
| logic [31:0] conv_result, addmul_result; | ||
| logic [3:0] conv_fpcsr, maxmin_fpcsr, addmul_fpcsr; | ||
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| //Instantiate the conversion module | ||
| bf16_conversion bf16_fp32_conversion_inst ( | ||
| .clk(clk), | ||
| .reset(reset), | ||
| .enable(conv_enable), | ||
| .operation(operation), // Pass the operation code | ||
| .operand(operand_a), // Pass the operand | ||
| .result(conv_result), // Receive the result | ||
| .fpcsr(conv_fpcsr) // Receive the FPCSR status | ||
| ); | ||
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| // Instantiate the max/min module | ||
| bf16_minmax maxmin_module ( | ||
| .clk(clk), | ||
| .reset(reset), | ||
| .enable(maxmin_enable), | ||
| .operand_a(operand_a[15:0]), | ||
| .operand_b(operand_b[15:0]), | ||
| .operation(operation), | ||
| .result(maxmin_result), | ||
| .fpcsr(maxmin_fpcsr) | ||
| ); | ||
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| // Instantiate the add/mul module | ||
| bf16_fma_op addmul_module ( | ||
| .clk(clk), | ||
| .reset(reset), | ||
| .en(addmul_enable), | ||
| .op_a(operand_a), | ||
| .op_b(operand_b), | ||
| .op_c(operand_c), | ||
| .oper(operation), | ||
| .result(addmul_result), | ||
| .fpcsr(addmul_fpcsr) | ||
| ); | ||
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| // // Conversion Operations | ||
| // 4'b0000: conv_enable = 1; // BF16 to FP32 Conversion | ||
| // 4'b0001: conv_enable = 1; // FP32 to BF16 Conversion | ||
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| // // Max/Min Operations | ||
| // 4'b0010: maxmin_enable = 1; // Max | ||
| // 4'b0011: maxmin_enable = 1; // Min | ||
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| // // Add/Mul Operations | ||
| // 4'b0100: addmul_enable = 1; // Add | ||
| // 4'b0101: addmul_enable = 1; // Mul | ||
| // 4'b0110: addmul_enable = 1; // Sub | ||
| // 4'b0111: addmul_enable = 1; // Fused Multiply-Add (FMADD) | ||
| // 4'b1000: addmul_enable = 1; // Fused Multiply-Subtract (FMSUB) | ||
| // 4'b1001: addmul_enable = 1; // Fused Negative Multiply-Add (FMNADD) | ||
| // 4'b1010: addmul_enable = 1; // Fused Negative Multiply-Subtract (FMNSUB) | ||
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| assign conv_enable = !operation[3] & !operation[2] & !operation[1]; | ||
| assign maxmin_enable = !operation[3] & !operation[2] & operation[1]; | ||
| assign addmul_enable = operation[3] | operation[2]; | ||
| assign result = ({32{conv_enable}} & conv_result) | ({32{maxmin_enable}} & maxmin_result) | ({32{addmul_enable}} & addmul_result); | ||
| assign fpcsr = ({32{conv_enable}} & conv_fpcsr) | ({32{maxmin_enable}} & maxmin_fpcsr) | ({32{addmul_enable}} & addmul_fpcsr); | ||
| assign valid = enable && (conv_enable || maxmin_enable || addmul_enable); | ||
| // Result and FPCSR aggregation | ||
| //always @(posedge clk) begin | ||
| // valid = enable && (conv_enable || maxmin_enable || addmul_enable); | ||
| // conv_enable = !operation[3] & !operation[2] & !operation[1]; | ||
| // maxmin_enable = !operation[3] & !operation[2] & operation[1]; | ||
| // addmul_enable = operation[3] | operation[2]; | ||
| // if (!reset) begin | ||
| // if (conv_enable) begin | ||
| // result = conv_result; | ||
| // fpcsr = conv_fpcsr; | ||
| // end else if (maxmin_enable) begin | ||
| // result = maxmin_result; | ||
| // fpcsr = maxmin_fpcsr; | ||
| // end else if (addmul_enable) begin | ||
| // result = addmul_result; | ||
| // fpcsr = addmul_fpcsr; | ||
| // end | ||
| // end else begin | ||
| // result = 32'h0; | ||
| // fpcsr = 4'h0; | ||
| // end | ||
| //end | ||
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| endmodule | ||
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,108 @@ | ||
| `timescale 1ns / 1ps | ||
| ////////////////////////////////////////////////////////////////////////////////// | ||
| // Company: | ||
| // Engineer: | ||
| // | ||
| // Create Date: 12/06/2023 06:19:26 PM | ||
| // Design Name: | ||
| // Module Name: conversion_bf16 | ||
| // Project Name: | ||
| // Target Devices: | ||
| // Tool Versions: | ||
| // Description: | ||
| // | ||
| // Dependencies: | ||
| // | ||
| // Revision: | ||
| // Revision 0.01 - File Created | ||
| // Additional Comments: | ||
| // | ||
| ////////////////////////////////////////////////////////////////////////////////// | ||
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| module bf16_conversion( | ||
| input logic clk, | ||
| input logic reset, | ||
| input logic enable, // Enable signal for conversion operations | ||
| input logic [3:0] operation, // 4-bit operation code | ||
| input logic [31:0] operand, // Universal operand for both BF16 and FP32 | ||
| output logic [31:0] result, // Result, either BF16 or FP32 | ||
| output logic [3:0] fpcsr // Floating Point Control and Status Register | ||
| ); | ||
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| // Define operation codes for conversions | ||
| localparam BF16_TO_FP32_OP = 4'b0000; | ||
| localparam FP32_TO_BF16_OP = 4'b0001; | ||
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| wire bf16tofp32_en; | ||
| wire fp32tobf16_en; | ||
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| // Internal signals for the submodules | ||
| wire [15:0] bf16_result; | ||
| wire [31:0] fp32_result; | ||
| wire [3:0] bf16_fpcsr; | ||
| wire [3:0] fp32_fpcsr; | ||
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| assign bf16tofp32_en = enable & (operation == BF16_TO_FP32_OP); | ||
| assign fp32tobf16_en = enable & (operation == FP32_TO_BF16_OP); | ||
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| // Instantiate bf16_to_fp32 module | ||
| bf16_to_fp32 bf16_to_fp32_inst ( | ||
| .clk(clk), | ||
| .reset(reset), | ||
| .instruction_enable(bf16tofp32_en), | ||
| .operand_a(operand[15:0]), | ||
| .result(fp32_result), | ||
| .fpcsr(bf16_fpcsr) | ||
| ); | ||
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| // Instantiate fp32_to_bf16 module | ||
| fp32_to_bf16 fp32_to_bf16_inst ( | ||
| .clk(clk), | ||
| .reset(reset), | ||
| .instruction_enable(fp32tobf16_en), | ||
| .operand_a(operand), | ||
| .result(bf16_result), | ||
| .fpcsr(fp32_fpcsr) | ||
| ); | ||
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| // Logic to select the appropriate output based on operation | ||
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| assign result = (operation == BF16_TO_FP32_OP) ? fp32_result : | ||
| (operation == FP32_TO_BF16_OP) ? {16'h0000, bf16_result} : | ||
| 32'h00000000; | ||
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| assign fpcsr = (operation == BF16_TO_FP32_OP) ? bf16_fpcsr : | ||
| (operation == FP32_TO_BF16_OP) ? fp32_fpcsr : | ||
| 4'b0000; | ||
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| // always @(posedge clk ) begin | ||
| // if(enable)begin | ||
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| // case (operation) | ||
| // BF16_TO_FP32_OP: begin | ||
| // result = fp32_result; | ||
| // fpcsr = bf16_fpcsr; | ||
| // end | ||
| // FP32_TO_BF16_OP: begin | ||
| // result = {16'h0000, bf16_result}; // Zero-extend BF16 result to 32 bits | ||
| // fpcsr = fp32_fpcsr; | ||
| // end | ||
| // default: begin | ||
| // result = 32'h00000000; | ||
| // fpcsr = 4'b0000; | ||
| // end | ||
| // endcase | ||
| // end | ||
| // end | ||
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| endmodule | ||
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