Xilinx Data Center Recipes

The documentation in this repository is distributed under a Creative Commons Attribution 4.0 International License.

The content of this repository has as objective to provide recipes about the flow employed to work with Alveo boards or the Amazon FPGA instances (F1). Although there exists getting started tutorials provided by Xilinx and Amazon, they are intended as a first approach, with one-time configurations performed in the middle, missing steps or the absence of general troubleshooting. Moreover, they could be not suitable for subsequent executions, where you only want instructions without long explanations (recipes).

Recipes

• Alveo Workflow
• AWS Configurations
• AWS Workflow
• Vitis RTL Flow

Useful links

Alveo

• Getting Started with Alveo Data Center Accelerator Cards (pdf)

AWS EC2 F1

• AWS FPGA (repo)
• Vitis AWS F1 Developer Labs (repo)
• Developing on AWS F1 with SDAccel and RTL Kernels (videos):
  • Introduction to AWS F1 and the SDAccel Development Environment (video, 30:44)
  • AWS F1 Hardware Specification and Requirements (video, 9:21)
  • Packaging Existing RTL IP for AWS F1 (video, 41:37)
  • Running a Host-side Application with an RTL Kernel (video, 31:10)
• AWS FPGA discussion (forum)

Vitis

• Vitis tutorials (repo, doc) (formerly SDAccel tutorials)
• Vitis In-Depth Tutorials (repo)
• Vitis Accel Examples (repo, doc) (formerly SDAccel examples)
• Vitis libraries (repo, doc)
• Vitis Unified Software Platform Documentation - Application Acceleration Development (pdf)

Vitis-AI

• Vitis AI (repo) (formerly ML Suite)
• Vitis AI tutorials (repo)
• Vitis AI User Guide (pdf)

UltraFast DesignMethodology

• UltraFast Design Methodology Guide for the Vivado Design Suite (pdf)
• UltraFast Design Methodology Guidelines For Predicatble Success (video, 54:31)