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Recent commit `d08d53346b993431e309797d5e6de8da20147c3c` qca-ssdk: support selecting PCS channel for PORT3 on IPQ6018 Ends up breaking patch. Updated to address the following: Applying patch 102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch patching file include/init/ssdk_dts.h Hunk #1 succeeded at 99 (offset -2 lines). Hunk #2 succeeded at 161 (offset -3 lines). patching file src/adpt/cppe/adpt_cppe_portctrl.c patching file src/adpt/hppe/adpt_hppe_uniphy.c Hunk #1 succeeded at 1152 (offset 30 lines). Hunk #2 succeeded at 1161 (offset 30 lines). patching file src/init/ssdk_dts.c Hunk #1 FAILED at 279. Hunk #2 succeeded at 305 (offset -8 lines). Hunk #3 succeeded at 1310 (offset -16 lines). 1 out of 3 hunks FAILED -- rejects in file src/init/ssdk_dts.c Patch 102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch does not apply (enforce with -f)
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Original file line number | Diff line number | Diff line change |
---|---|---|
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@@ -22,28 +22,24 @@ Signed-off-by: Mantas Pucka <[email protected]> | |
src/init/ssdk_dts.c | 27 +++++++++++++++++++++++++++ | ||
4 files changed, 32 insertions(+), 8 deletions(-) | ||
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||
diff --git a/include/init/ssdk_dts.h b/include/init/ssdk_dts.h | ||
index 00fa4c1..210c788 100755 | ||
--- a/include/init/ssdk_dts.h | ||
+++ b/include/init/ssdk_dts.h | ||
@@ -101,6 +101,7 @@ typedef struct | ||
@@ -99,6 +99,7 @@ typedef struct | ||
a_uint32_t emu_chip_ver; /*only valid when is_emulation is true*/ | ||
a_uint32_t clk_mode; | ||
a_uint32_t pcie_hw_base; | ||
+ a_uint32_t port3_pcs_channel; | ||
} ssdk_dt_cfg; | ||
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||
#define SSDK_MAX_NR_ETH 6 | ||
@@ -163,6 +164,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t index); | ||
@@ -160,6 +161,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t | ||
struct device_node *ssdk_dts_node_get(a_uint32_t dev_id); | ||
struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id); | ||
struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id); | ||
+a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id); | ||
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||
int ssdk_switch_device_num_init(void); | ||
void ssdk_switch_device_num_exit(void); | ||
diff --git a/src/adpt/cppe/adpt_cppe_portctrl.c b/src/adpt/cppe/adpt_cppe_portctrl.c | ||
index 00d0404..6b32f79 100755 | ||
--- a/src/adpt/cppe/adpt_cppe_portctrl.c | ||
+++ b/src/adpt/cppe/adpt_cppe_portctrl.c | ||
@@ -33,6 +33,7 @@ | ||
|
@@ -54,7 +50,7 @@ index 00d0404..6b32f79 100755 | |
#include "adpt.h" | ||
#include "adpt_hppe.h" | ||
#include "adpt_cppe_portctrl.h" | ||
@@ -60,8 +61,7 @@ _adpt_cppe_port_mux_mac_set(a_uint32_t dev_id, fal_port_t port_id, | ||
@@ -60,8 +61,7 @@ _adpt_cppe_port_mux_mac_set(a_uint32_t d | ||
case SSDK_PHYSICAL_PORT3: | ||
case SSDK_PHYSICAL_PORT4: | ||
if (mode0 == PORT_WRAPPER_PSGMII) { | ||
|
@@ -64,11 +60,9 @@ index 00d0404..6b32f79 100755 | |
cppe_port_mux_ctrl.bf.port3_pcs_sel = | ||
CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4; | ||
cppe_port_mux_ctrl.bf.port4_pcs_sel = | ||
diff --git a/src/adpt/hppe/adpt_hppe_uniphy.c b/src/adpt/hppe/adpt_hppe_uniphy.c | ||
index 5e36602..bad1eab 100644 | ||
--- a/src/adpt/hppe/adpt_hppe_uniphy.c | ||
+++ b/src/adpt/hppe/adpt_hppe_uniphy.c | ||
@@ -1122,9 +1122,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index) | ||
@@ -1152,9 +1152,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin | ||
{ | ||
a_uint32_t i; | ||
sw_error_t rv = SW_OK; | ||
|
@@ -78,7 +72,7 @@ index 5e36602..bad1eab 100644 | |
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||
union uniphy_mode_ctrl_u uniphy_mode_ctrl; | ||
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||
@@ -1134,9 +1131,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uint32_t dev_id, a_uint32_t uniphy_index) | ||
@@ -1164,9 +1161,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin | ||
SSDK_DEBUG("uniphy %d is psgmii mode\n", uniphy_index); | ||
#if defined(CPPE) | ||
if (adpt_ppe_type_get(dev_id) == CPPE_TYPE) { | ||
|
@@ -89,25 +83,23 @@ index 5e36602..bad1eab 100644 | |
SSDK_INFO("cypress uniphy %d is qca8072 psgmii mode\n", uniphy_index); | ||
rv = __adpt_cppe_uniphy_mode_set(dev_id, uniphy_index, | ||
PORT_WRAPPER_PSGMII); | ||
diff --git a/src/init/ssdk_dts.c b/src/init/ssdk_dts.c | ||
index 686b6d2..70b0a09 100644 | ||
--- a/src/init/ssdk_dts.c | ||
+++ b/src/init/ssdk_dts.c | ||
@@ -279,6 +279,13 @@ struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id) | ||
@@ -272,6 +272,13 @@ struct clk *ssdk_dts_cmnclk_get(a_uint32 | ||
return cfg->cmnblk_clk; | ||
} | ||
|
||
+a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id) | ||
+{ | ||
+ ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]; | ||
+ | ||
+ | ||
+ return cfg->port3_pcs_channel; | ||
+} | ||
+ | ||
#ifndef BOARD_AR71XX | ||
#if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)) | ||
static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id, | ||
@@ -313,6 +320,25 @@ static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id, | ||
struct device_node *switch_node, ssdk_init_cfg *cfg) | ||
@@ -305,6 +312,25 @@ static void ssdk_dt_parse_mac_mode(a_uin | ||
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||
return; | ||
} | ||
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@@ -117,7 +109,7 @@ index 686b6d2..70b0a09 100644 | |
+{ | ||
+ const __be32 *port3_pcs_channel; | ||
+ a_uint32_t len = 0; | ||
+ | ||
+ | ||
+ port3_pcs_channel = of_get_property(switch_node, "port3_pcs_channel", &len); | ||
+ if (!port3_pcs_channel) { | ||
+ ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel = 2; | ||
|
@@ -133,14 +125,11 @@ index 686b6d2..70b0a09 100644 | |
#ifdef IN_UNIPHY | ||
static void ssdk_dt_parse_uniphy(a_uint32_t dev_id) | ||
{ | ||
@@ -1307,6 +1333,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg *cfg, a_uint32_t num, a_uint32_t *dev_id) | ||
@@ -1291,6 +1317,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg * | ||
rv = ssdk_dt_parse_access_mode(switch_node, ssdk_dt_priv); | ||
SW_RTN_ON_ERROR(rv); | ||
ssdk_dt_parse_mac_mode(*dev_id, switch_node, cfg); | ||
+ ssdk_dt_parse_port3_pcs_channel(*dev_id, switch_node, cfg); | ||
ssdk_dt_parse_mdio(*dev_id, switch_node, cfg); | ||
ssdk_dt_parse_port_bmp(*dev_id, switch_node, cfg); | ||
ssdk_dt_parse_interrupt(*dev_id, switch_node); | ||
-- | ||
2.7.4 | ||
|