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Removed content to avoid confusion.
Updated RISC V Cores and SoCs (markdown)
Add Minerva from LambdaConcept
Added "OpenPiton + Ariane" SoC
Added Western Digital's SweRV EH1 core
Fix typo
Add SERV to list
fix RV32M1 availability date
fix columns for RV32M1
Add RV32M1, which is available for preorder in VEGAboard dev board
Add MR1 core
Moved PULPino from cores to SoCs. Added PULPissimo to SoCs. Added to cores: RI5CY, Zero-riscy, Ariane, Riscy Processors
Add Kendryte K210 physical chip
Add PicoRV32 core, PicoSoC, and Icicle
Created RISC V Cores and SoCs (markdown)
Destroyed RISC V Cores and SoCs (markdown)
Fix table
Change chips to table
Change SoCs to table
Change cores to table