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RISC V Cores and SoCs
Michael Gielda edited this page Nov 21, 2018
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This document captures the status of various cores and SoCs that endeavor to implement the RISC-V specification. Note that none of these cores/SoCs have passed the in-development RISC-V compliance suite.
Please add to the list and fix inaccuracies.
Name | Links | Priv. spec | User spec | License | Maintainers |
---|---|---|---|---|---|
rocket | GitHub | 1.11-draft | 2.3-draft | BSD | SiFive, UCB Bar |
freedom | GitHub | 1.11-draft | 2.3-draft | BSD | SiFive |
Berkeley Out-of-Order Machine (BOOM) | GitHub | 1.11-draft | 2.3-draft | BSD | Esperanto, UCB Bar |
ORCA | GitHub | RV32IM | BSD | VectorBlox | |
PULPino | Website,GitHub | Solderpad Hardware License v. 0.51 | ETH Zurich, Università di Bologna | ||
OPenV/mriscv | GitHub | RV32I(?) | MIT | OnChipUIS | |
VexRiscv | GitHub | RV32I[M][C] | MIT | SpinalHDL | |
Roa Logic RV12 | GitHub | 1.9.1 | 2.1 | Non-Commercial License | Roa Logic |
SCR1 | GitHub | 1.10 | 2.2, RV32I/E[MC] | Solderpad Hardware License v. 0.51 | Syntacore |
Hummingbird E200 | GitHub | 1.10 | 2.2, RV32IMAC | Apache 2.0 | Bob Hu |
Shakti | Website,GitHub | 1.10 | 2.2, RV64IMAFD | BSD | IIT Madras |
ReonV | GitHub | GPL v3 |
- Maintainer(s): SiFive, UCB BAR
- License: BSD
- Repository URL: https://github.com/freechipsproject/rocket-chip
- Core: Rocket
- Links: FPGA-Accelerated Simulation Platform on Cloud FPGAs with Rocket Chip support (FireSim): https://fires.im, https://github.com/firesim/firesim
- Maintainer(s): LowRISC CIC
- License: BSD
- Repository URL: https://github.com/lowRISC/lowrisc-chip
- Core: RV32IM
- Maintainer(s): SpinalHDL
- License: MIT License
- Repository URL: https://github.com/SpinalHDL/VexRiscv#briey-soc
- Core: VexRiscv
- Interconnects: AXI4 / APB3
- Maintainer(s): AleksandarKostovic
- License: MIT
- Repository URL: https://github.com/AleksandarKostovic/Riscy-SoC
- Core: RV64I
- Maintainer(s): RTimothyEdwards, mkkassem (efabless.com)
- License: ISC
- Repository URL: https://github.com/efabless/picorv32-soc-raven
- Core: PICORV32
- Links: https://ef.link/picorv32-soc-raven, http://ef.link/raven-soc-hackster
Include a chip if it has been fabricated and is either available for sale, available for preorder, or running production workloads internally, and if it has at least one RISC-V hard core (no FPGAs, but non-"SoC" products with controller cores are allowed).
- Vendor: SiFive
- Core: E31
- ISA: RV32IMAC
- Availability: public since 2016Q4
- Used for: HiFive1 Arduino board
- Links: https://static.dev.sifive.com/FE310-G000.pdf
- Vendor: SiFive
- CORE: U54 (4 cores), E51 (1 management core)
- ISA: RV64GC (application cores), RV64IMAC (management core)
- Used for: HiFive Unleashed development board
- Availability: announced 2018Q1, available for preorder
- Links: https://www.sifive.com/products/hifive-unleashed/
- Vendor: GreenWaves Technologies
- Core: PULP / 1 + 8 RI5CY
- ISA: RV32IMC (+ Priviledged and custom ISA extensions)
- Availability: public since 2018Q1
- Used for: GAPuino development board
- Links: https://greenwaves-technologies.com/en/gap8-product/