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RISC V Cores and SoCs

Michael Gielda edited this page Nov 21, 2018 · 84 revisions

RISC-V Cores and SoC Overview

This document captures the status of various cores and SoCs that endeavor to implement the RISC-V specification. Note that none of these cores/SoCs have passed the in-development RISC-V compliance suite.

Please add to the list and fix inaccuracies.

Name Links Priv. spec User spec License Maintainers
rocket GitHub 1.11-draft 2.3-draft BSD SiFive, UCB Bar
freedom GitHub 1.11-draft 2.3-draft BSD SiFive
Berkeley Out-of-Order Machine (BOOM) GitHub 1.11-draft 2.3-draft BSD Esperanto, UCB Bar
ORCA GitHub RV32IM BSD VectorBlox
PULPino Website,GitHub Solderpad Hardware License v. 0.51 ETH Zurich, Università di Bologna
OPenV/mriscv GitHub RV32I(?) MIT OnChipUIS
VexRiscv GitHub RV32I[M][C] MIT SpinalHDL
Roa Logic RV12 GitHub 1.9.1 2.1 Non-Commercial License Roa Logic
SCR1 GitHub 1.10 2.2, RV32I/E[MC] Solderpad Hardware License v. 0.51 Syntacore
Hummingbird E200 GitHub 1.10 2.2, RV32IMAC Apache 2.0 Bob Hu
Shakti Website,GitHub 1.10 2.2, RV64IMAFD BSD IIT Madras
ReonV GitHub GPL v3

SoCs

Rocket Chip

LowRISC

Briey

Riscy

Raven

Chips

Include a chip if it has been fabricated and is either available for sale, available for preorder, or running production workloads internally, and if it has at least one RISC-V hard core (no FPGAs, but non-"SoC" products with controller cores are allowed).

FE310-G000

Freedom U540

  • Vendor: SiFive
  • CORE: U54 (4 cores), E51 (1 management core)
  • ISA: RV64GC (application cores), RV64IMAC (management core)
  • Used for: HiFive Unleashed development board
  • Availability: announced 2018Q1, available for preorder
  • Links: https://www.sifive.com/products/hifive-unleashed/

GAP8

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