make unimplemented mode bits ROZ instead of WARL

riscvarchive · Jul 24, 2023 · 2c25f77 · 2c25f77
1 parent 9fdd94d
commit 2c25f77
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/csrs.adoc b/csrs.adoc
@@ -23,7 +23,7 @@ mcyclecfg and minstretcfg are 64-bit registers that configure privilege mode fil
 
 When all __x__INH bits are zero, event counting is enabled in all modes.
 
-For each bit in 61:58, if the associated privilege mode is not implemented, the bit is WARL.  Bits 57:56 are reserved for possible future modes.  
+For each bit in 61:58, if the associated privilege mode is not implemented, the bit is read-only zero.  Bits 57:56 are reserved for possible future modes.  
 
 For RV32, bits 63:32 of mcyclecfg can be accessed via the mcyclecfgh CSR, and bits 63:32 of minstretcfg can be accessed via the minstretcfgh CSR.