This repository has been archived by the owner on Jan 11, 2019. It is now read-only.
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The risc-v qemu recipe wasn't pointing at a valid commit from the
github.com/riscv/riscv-qemu.git repository.
Tweak how the QEMU_TARGETS variable is populated in order to pick a valid
target. IOW riscv -> riscv64.
Signed-off-by: Trevor Woerner [email protected]