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Implement Zicbom, Zicboz (cbo.flush, cbo.inval, cbo.zero) #455
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Shouldn't there be encoding and assembly information at least? It might also be useful to calculate the address and pass it to a built-in function so that it could be logged (e.g., to check that some code's prefetch instruction refers to the correct address), along with a comment noting that no exceptions are taken if something goes wrong. |
That's a good point... I think it can be a separate PR though if anyone wants to tackle it. |
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HI, |
Yes it is - it's based on the older one (#137) with some fixes. As far as I am concerned it is ready to merge; it's just waiting on review. No ETA I'm afraid - not many people are actively reviewing PRs and unfortunately nobody is paid to do it currently. (IMO RVI should hire someone to do this but that's an ongoing discussion.) |
I'll review it.
However, I see that there are some conflicts that need to be resolved.
Bill Mc.
…On Tue, Jul 16, 2024 at 6:18 AM Tim Hutt ***@***.***> wrote:
Yes it is - it's based on the older one (#137
<#137>) with some fixes. As far
as I am concerned it is ready to merge; it's just waiting on review.
No ETA I'm afraid - not many people are actively reviewing PRs and
unfortunately nobody is paid to do it currently. (IMO RVI should hire
someone to do this but that's an ongoing discussion.)
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@tim Hutt ***@***.***> , how did you test your
implementation?
Bill Mc.
…On Tue, Jul 16, 2024 at 7:45 AM Bill McSpadden ***@***.***> wrote:
I'll review it.
However, I see that there are some conflicts that need to be resolved.
Bill Mc.
On Tue, Jul 16, 2024 at 6:18 AM Tim Hutt ***@***.***> wrote:
> Yes it is - it's based on the older one (#137
> <#137>) with some fixes. As far
> as I am concerned it is ready to merge; it's just waiting on review.
>
> No ETA I'm afraid - not many people are actively reviewing PRs and
> unfortunately nobody is paid to do it currently. (IMO RVI should hire
> someone to do this but that's an ongoing discussion.)
>
> —
> Reply to this email directly, view it on GitHub
> <#455 (comment)>,
> or unsubscribe
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> You are receiving this because you are subscribed to this thread.Message
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Bill McSpadden
Formal Verification Engineer
RISC-V International
mobile: 503-807-9309
|
Thanks, I've rebased and fixed the conflicts. It's been tested by running against our A730 chip with the following tests:
The first two only test |
Great! I'm glad to see that you found the zero.S test in riscv-tests.
I was going to point you to it, but as usual, you are ahead of the game.
Bill Mc.
…On Tue, Jul 16, 2024 at 9:06 AM Tim Hutt ***@***.***> wrote:
Thanks, I've rebased and fixed the conflicts.
It's been tested by running against our A730 chip with the following tests:
- cbo.zero-01.S from riscv-arch-test
- zero.S from riscv-tests
- A very basic directed test we wrote that does some stores and loads
combined with the CBO instructions and CSR settings.
- STING - it's not really clear exactly what they test (the
descriptions are unhelpfully short like "Test for cmo instruction -
CBO.FLUSH") but they're generally pretty good.
The first two only test cbo.zero; I'm not sure why they didn't add tests
for the other instructions.
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Thanks for the review @jrtc27 ! |
HI, It'll be great if this can be reviewed and closed. |
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Adding a gentle nudge to animesh211's request for this to be merged and closed. |
Note that Zicbop (prefetch hints) does not need to be implemented because all it does is label some existing base instructions as prefetch hints.
I rebased this and updated it to use the new
should be this
however I left it as it was just so we can get this in. @billmcspadden-riscv any objection to merging this? I think it has been ready with no objections for a long time. |
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LGTM
Thanks! |
Note that Zicbop (prefetch hints) does not need to be implemented because all it does is label some existing base instructions as prefetch hints.
Also I have not wired up the enable flags to the emulators because it is rather tedious (and will hopefully be replaced by riscv-config at some point).