Merge branch 'main' of github.com:mehnadnerd/riscv-zalasr

chapter2.adoc

@@ -45,7 +45,7 @@ If the address is not naturally aligned, an address-misaligned exception or an a
 The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.
 If the Zam standard extension is implemented, the address is not required to be aligned and the weaker atomicity guarantee provided by Zam applies.
 The versions without the _aq_ bit set are RESERVED.
-RV32 should not implement the d and q variants and RV64 should not implement the q variant.
+RV32 shall not implement the d and q variants and RV64 shall not implement the q variant.
 
 funct5 for this instruction is 00110.
 
@@ -159,7 +159,7 @@ If the address is not naturally aligned, an address-misaligned exception or an a
 The access-fault exception can be generated for a memory access that would otherwise be able to complete except for the misalignment, if the misaligned access should not be emulated.
 If the Zam standard extension is implemented, the address is not required to be aligned and the weaker atomicity guarantee provided by Zam applies.
 The versions without the _rl_ bit set are RESERVED.
-RV32 should not implement the d and q variants and RV64 should not implement the q variant.
+RV32 shall not implement the d and q variants and RV64 shall not implement the q variant.
 
 funct5 for this instruction is 00111.
 
@@ -246,4 +246,4 @@ mapping clause assembly = STORERL(aq, rl, rs2, rs1, size)
 --
 
 
-// store-ordered funct5 = 00111
+// store-ordered funct5 = 00111