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Remove outdated comment
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Resolves #1450
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aswaterman committed Jun 11, 2024
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Expand Up @@ -1586,13 +1586,6 @@ include::images/bytefield/hpmevents.adoc[]
The `mhpmcounters` are *WARL* registers that support up to 64 bits of
precision on RV32 and RV64.

[NOTE]
====
A future revision of this specification will define a mechanism to
generate an interrupt when a hardware performance monitor counter
overflows.
====

When XLEN=32, reads of the `mcycle`, `minstret`, `mhpmcounter__n__`, and `mhpmevent__n__`
CSRs return bits 31-0 of the corresponding register, and writes change
only bits 31-0; reads of the `mcycleh`, `minstreth`, `mhpmcounter__n__h`, and `mhpmevent__n__h`
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