attempt at listing some system rules with examples #401
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arichardson
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Oct 3, 2024
arichardson
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Oct 3, 2024
Co-authored-by: Alexander Richardson <[email protected]> Signed-off-by: Andres Amaya Garcia <[email protected]>
andresag01
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Oct 4, 2024
Signed-off-by: Andres Amaya Garcia <[email protected]>
Co-authored-by: Alexander Richardson <[email protected]> Signed-off-by: Andres Amaya Garcia <[email protected]>
arichardson
reviewed
Oct 4, 2024
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| There are two types of bus connections used in chips which contain CHERI CPUs: | ||
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| . Tag-aware busses, where the bus protocol is extended to carry the tag along with the data. This is typically done using a user defined bit in the protocol. |
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| . Tag-aware busses, where the bus protocol is extended to carry the tag along with the data. This is typically done using a user defined bit in the protocol. | |
| . Tag-aware busses, where the bus protocol is extended to carry the tag along with the data. This is typically done using user defined bits in the protocol. |
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| There are, or will soon be, a wide range of CHERI systems in existence from tiny IoT devices up to server chips. | ||
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| There are two types of bus connections used in chips which contain CHERI CPUs: |
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| There are two types of bus connections used in chips which contain CHERI CPUs: | |
| There are two types of bus connections used in SoCs which contain CHERI CPUs: |
| . Tag-aware busses, where the bus protocol is extended to carry the tag along with the data. This is typically done using a user defined bit in the protocol. | ||
| .. These busses will read tags from memory (if tags are present in the target memory) and return them to the requestor. | ||
| .. These busses will write the tag to memory as an extension of the data write. | ||
| . Non-tag aware busses, i.e. normal non-CHERI aware busses. |
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| . Non-tag aware busses, i.e. normal non-CHERI aware busses. | |
| . Non-tag aware busses, i.e. current non-CHERI aware busses. |
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I've put these into #409
tariqkurd-repo
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Oct 9, 2024
Something which came up in RVI discussions is how to build CHERI systems, so this section adds some system guidelines. --------- Signed-off-by: Andres Amaya Garcia <[email protected]> Co-authored-by: Andres Amaya Garcia <[email protected]> Co-authored-by: Alexander Richardson <[email protected]>
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Something which came up in RVI discussions is how to build CHERI systems, so this section adds some system guidelines.