add extra information into exception reporting

src/img/mtval2reg.edn

@@ -0,0 +1,14 @@
+[bytefield]
+----
+(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
+(def row-height 40)
+(def row-header-fn nil)
+(def left-margin 100)
+(def right-margin 100)
+(def boxes-per-row 32)
+(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1"])})
+
+(draw-box "Addr"   {:span 32})
+
+(draw-box "MXLEN" {:span 32 :borders {}})
+----

src/img/mtvalreg.edn

@@ -6,15 +6,17 @@
 (def left-margin 100)
 (def right-margin 100)
 (def boxes-per-row 32)
-(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "3" "4" "" "" "" "" "" "" "" "" "" "" "15" "16" "" "" "19" "20" "" "" "" "" "" "" "" "" "" "" "MXLEN-1"])})
+(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "3" "4" "" "" "" "" "9" "10" "" "" "" "" "15" "16" "" "" "19" "20" "" "" "" "" "" "" "" "" "" "" "MXLEN-1"])})
 
 (draw-box "Reserved"   {:span 12})
 (draw-box "TYPE"       {:span 4})
-(draw-box "Reserved"   {:span 12})
+(draw-box "Reserved"   {:span 6})
+(draw-box "CAP_IDX"    {:span 6})
 (draw-box "CAUSE"      {:span 4})
 
 (draw-box "MXLEN-20" {:span 12 :borders {}})
 (draw-box "4"        {:span 4 :borders {}})
-(draw-box "12"       {:span 12 :borders {}})
+(draw-box "6"        {:span 6 :borders {}})
+(draw-box "6"        {:span 6 :borders {}})
 (draw-box "4"        {:span 4 :borders {}})
 ----

src/img/stval2reg.edn

@@ -0,0 +1,14 @@
+[bytefield]
+----
+(defattrs :plain [:plain {:font-family "M+ 1p Fallback" :font-size 24}])
+(def row-height 40)
+(def row-header-fn nil)
+(def left-margin 100)
+(def right-margin 100)
+(def boxes-per-row 32)
+(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "" "MXLEN-1"])})
+
+(draw-box "Addr"   {:span 32})
+
+(draw-box "MXLEN" {:span 32 :borders {}})
+----

src/img/stvalreg.edn

@@ -6,15 +6,17 @@
 (def left-margin 100)
 (def right-margin 100)
 (def boxes-per-row 32)
-(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "3" "4" "" "" "" "" "" "" "" "" "" "" "15" "16" "" "" "19" "20" "" "" "" "" "" "" "" "" "" "" "SXLEN-1"])})
+(draw-column-headers {:height 20 :font-size 18 :labels (reverse ["0" "" "" "3" "4" "" "" "" "" "9" "10" "" "" "" "" "15" "16" "" "" "19" "20" "" "" "" "" "" "" "" "" "" "" "SXLEN-1"])})
 
 (draw-box "Reserved"   {:span 12})
 (draw-box "TYPE"       {:span 4})
-(draw-box "Reserved"   {:span 12})
+(draw-box "Reserved"   {:span 6})
+(draw-box "CAP_IDX"    {:span 6})
 (draw-box "CAUSE"      {:span 4})
 
 (draw-box "SXLEN-20" {:span 12 :borders {}})
 (draw-box "4"        {:span 4 :borders {}})
-(draw-box "12"       {:span 12 :borders {}})
+(draw-box "6"        {:span 6 :borders {}})
+(draw-box "6"        {:span 6 :borders {}})
 (draw-box "4"        {:span 4 :borders {}})
 ----

src/riscv-integration.adoc

@@ -771,6 +771,20 @@ xref:mtval-cheri-causes[xrefstyle=short] respectively.
 | 3-15                      | Reserved
 |==============================================================================
 
+.Encoding of CAP_IDX field
+[#mtval-cheri-cap-idx,width=65%,float="center",align="center",options=header,cols="30%,70%"]
+|==============================================================================
+| CHERI CAP_IDX Code        | Description
+| 0                         | Faulting cap was c0
+| 1                         | Faulting cap was c1
+| ...                       |
+| 30                        | Faulting cap was c30
+| 31                        | Faulting cap was c31
+| 32                        | Faulting cap was <<ddc>>
+| 33                        | Faulting cap was <<pcc>>
+| 34-63                     | Reserved
+|==============================================================================
+
 .Encoding of CAUSE field
 [#mtval-cheri-causes,width=55%,float="center",align="center",options=header]
 |==============================================================================
@@ -791,6 +805,24 @@ CHERI violations have the following order in priority:
 . Invalid address violation
 . Bounds violation (_Lowest_)
 
+[#mtval2,reftext="mtval2"]
+==== Machine Trap Value Register 2 (mtval2)
+
+The <<mtval2>> register is an MXLEN-bit read-write register, which is added as part of the
+Hypervisor extension. {cheri_base_ext_name} also requires the implementation of this CSR.
+
+When a CHERI fault is taken on any data memory access into into M-mode, <<mtval2>> is written
+with the MXLEN-bit address which caused the fault. This follows the existing rules for reporting
+load/store addresses to <<mtval>> from [riscv-priv-spec].
+This reported address can be used together with the CAP_IDX field of <<mtval>> to diagnose the
+authorising capability which caused the exception.
+
+<<mtval2>> is set to zero for all PCC faults, and follows the standard rules for non-CHERI exceptions.
+
+.Machine trap value register 2
+[#mtval2-format]
+include::img/mtval2reg.edn[]
+
 [#supervisor-level-csrs-section]
 === Supervisor-Level CSRs
 
@@ -993,10 +1025,23 @@ xref:stval-format[xrefstyle=short] to assist software in handling the trap.
 [#stval-format]
 include::img/stvalreg.edn[]
 
-TYPE is a CHERI-specific fault type that caused the exception while CAUSE
-is the cause of the fault. The possible CHERI types and causes are encoded as
-shown in xref:mtval-cheri-type[xrefstyle=short] and
-xref:mtval-cheri-causes[xrefstyle=short] respectively.
+The fields are identical to <<mtval>> for CHERI exceptions.
+
+[#stval2,reftext="stval2"]
+==== Supervisor Trap Value Register 2 (stval2)
+
+The <<stval2>> register is an SXLEN-bit read-write register.
+
+The CSR address is 0x14b.
+
+When a fault is taken into S-mode <<stval2>> is updated as for <<mtval2>> for all CHERI memory access traps.
+It is set to zero in all other cases.
+
+NOTE: This is not a standard RISC-V CSR, but <<mtval2>> is. 0x14b is the regular location for the CSR.
+
+.Supervisor trap value register 2
+[#stval2-format]
+include::img/stval2reg.edn[]
 
 === Unprivileged CSRs