Make CRE not a WARL field

[Timmmm]

Change the CRE bits so they are always writable, but the effective CRE depends on multiple values. This is significantly simpler to specify, avoids an entire cross-CSR WARL field (WARL fields are a pain), and removes some undefined behaviour (do the bits retain their values when they are read-only zero).

Fixes #331

Note, I deleted the text about SXLEN/UXLEN. Those didn't seem fully specified tbh, but I'll need to add them back somehow.

[arichardson]

As noted in #332, I'm fine with this change but I'd wait for others to comment before merging.

A few small comments inline.

[buxtonpaul]

Agree this makes implementation simpler (at least in Qemu), and addresses the undefined behaviour regarding if bits are cleared. But there still isn't a way for S/U mode code to know what the effective CRE is as it is dependent on registers they cannot read. Unless they try an instruction and catch the resulting exception.

[jrtc27]

Agree this makes implementation simpler (at least in Qemu), and addresses the undefined behaviour regarding if bits are cleared. But there still isn't a way for S/U mode code to know what the effective CRE is as it is dependent on registers they cannot read. Unless they try an instruction and catch the resulting exception.

That’s what the device tree or ACPI whatever is for.

[buxtonpaul]

Agree this makes implementation simpler (at least in Qemu), and addresses the undefined behaviour regarding if bits are cleared. But there still isn't a way for S/U mode code to know what the effective CRE is as it is dependent on registers they cannot read. Unless they try an instruction and catch the resulting exception.

That’s what the device tree or ACPI whatever is for.
That makes sense, I guess there aren't many use cases for dynamically changing the CRE for a running system.

[Timmmm]

I've updated it so now the text talks about "CHERI register access" being enabled/disabled rather than the CRE bits or effective CRE, because the former takes account of mstatus.MBE and XLEN<MXLEN which can also disable CHERI register access. Hopefully this makes sense!