Chapter 1 minor revision

Makefile

@@ -18,7 +18,7 @@ GEN_SCRIPT   = $(SCRIPTS_DIR)/generate_tables.py
 
 # Version and date
 DATE    ?= $(shell date +%Y-%m-%d)
-VERSION ?= v0.7.0
+VERSION ?= v0.8.0
 REVMARK ?= Draft
 
 # URLs for downloaded CSV files

src/contributors.adoc

@@ -15,6 +15,7 @@ This RISC-V specification has been contributed to directly or indirectly by:
 * Alexandre Joannou <[email protected]>
 * Tariq Kurd <[email protected]>
 * Ben Laurie <[email protected]>
+* Marno van der Maas <[email protected]>
 * A. Theodore Markettos <[email protected]>
 * David McKay <[email protected]>
 * Jamie Melling <[email protected]>

src/introduction.adoc

@@ -38,8 +38,8 @@ address that is extended with metadata to protect its integrity, limit how it
 is manipulated, and control its use. This metadata includes:
 
 *  an out-of-band _tag_ implementing strong integrity protection
-(differentiating valid and invalid capabilities), This prevents confusion
-between data and capabilities.
+(differentiating valid and invalid capabilities) that prevents confusion
+between data and capabilities
 * _bounds_ limiting the range of addresses that may be dereferenced
 * _permissions_ controlling the specific operations that may be performed
 * _sealing_ which is used to support higher-level software encapsulation
@@ -59,7 +59,7 @@ Protection properties for capabilities include the ISA ensuring that
 capabilities are always derived via valid manipulations of other capabilities
 (_provenance_), that corrupted in-memory capabilities cannot be dereferenced
 (_integrity_), and that rights associated with capabilities shall only ever be
-equal or less permissive (_monotonicity_).Tampering or modifying capabilities
+equal or less permissive (_monotonicity_). Tampering or modifying capabilities
 in an attempt to elevate their rights will yield an invalid capability as the
 tag will be cleared. Attempting to dereference via an invalid capability
 will result in a hardware exception.
@@ -83,18 +83,18 @@ extensions to support CHERI alongside RISC-V:
 
 {cheri_base_ext_name}:: Introduces key, minimal CHERI concepts and features to
 the RISC-V ISA. The resulting extended ISA is not
-backwards-compatible with RISC-V
+backwards-compatible with RISC-V.
 {cheri_legacy_ext_name}:: Extends {cheri_base_ext_name} with features to ensure
 that the ISA extended with CHERI allows backwards binary compatibility with
 RISC-V.
 It also adds a mode bit in the encoding of capabilities to
 allow changing the current CHERI execution mode using indirect jump
-instructions
+instructions.
 {cheri_pte_ext_name}:: CHERI extension for RISC-V harts supporting page-based
-virtual-memory
+virtual-memory.
 {cheri_vectorcap_ext_name}:: CHERI extension for the RISC-V Vector (V)
 extension. It adds support for storing CHERI capabilities in
-vector registers, intended for vectorised memory copying
+vector registers, intended for vectorised memory copying.
 {tid_ext_name}:: Extension for supporting thread identifiers. This extension
 improves software compartmentalization on CHERI systems.