Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Mode flag value for infinite cap isn't specified #13

Closed
Timmmm opened this issue Jan 22, 2024 · 1 comment · Fixed by #19
Closed

Mode flag value for infinite cap isn't specified #13

Timmmm opened this issue Jan 22, 2024 · 1 comment · Fixed by #19
Labels
documentation Improvements or additions to documentation enhancement New feature or request

Comments

@Timmmm
Copy link
Contributor

Timmmm commented Jan 22, 2024

Zcheri_mode adds a M field to the cap. The NULL and Infinite Capabilities section specifies that the null cap is all zeros, so presumably that applies to M too. It doesn't say what M should be for the infinite cap.

I would guess it should also be zero since the mode doesn't form part of the null <-> infinite permission spectrum, but it would be good if it said that.
@arichardson arichardson added documentation Improvements or additions to documentation enhancement New feature or request labels Jan 22, 2024
@arichardson
Copy link
Collaborator

That is a good point, even though the capability respresentation section states that these capabilities have zero in all bits, we might want to clarify that this also includes reserved bits and add a reserved table row.

Timmmm added a commit to Timmmm/riscv-cheri that referenced this issue Jan 23, 2024
@Timmmm
Specify value of mode bit in null/infinite caps
b84aae8 
* Specify that M is 0 in both the infinite and null caps.
* Add 'Reserved' row to null/infinite cap table
* Change ref text for <<infinite-cap>> from "Infinity" to "Infinite" since that's how it is referred to elsewhere.

Fixes riscv#13
@Timmmm Timmmm mentioned this issue Jan 23, 2024
Merged
arichardson pushed a commit to arichardson/riscv-cheri that referenced this issue Jan 30, 2024
@rpsene
Merge pull request riscv#13 from rpsene/main
a685cfa 
Upgrade the build process
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
documentation Improvements or additions to documentation enhancement New feature or request
Projects
None yet
Milestone
No milestone
Development

Successfully merging a pull request may close this issue.

Specify value of mode bit in null/infinite caps Timmmm/riscv-cheri
2 participants
@Timmmm @arichardson