editorial

src/iommu_sw_guidelines.adoc

@@ -253,6 +253,8 @@ Between a change to the first-stage PTE and when an invalidation command to
 invalidate the cached PTE is processed by the IOMMU, the IOMMU may use the
 old PTE value or the new PTE value.
 
+<<<
+
 ==== Accessed (A)/Dirty (D) bit updates and page promotions
 
 When IOMMU supports hardware-managed A and D bit updates, if software clears
@@ -310,6 +312,8 @@ the DevATC may be satisfied by the IOMMU from the IOATC, to ensure correct
 operation software must first invalidate the IOATC before sending
 invalidations to the DevATC.
 
+<<<
+
 ==== Caching invalid entries
 
 This specification does not allow the caching of first/second-stage PTEs whose