Merge pull request #323 from ved-rivos/0520_1

Add missing did too wide check to inval_pdt
riscv-non-isa · May 20, 2024 · 40367b0 · 40367b0
2 parents f82f78b + ca1dad2
commit 40367b0
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diff --git a/iommu_ref_model/libiommu/src/iommu_command_queue.c b/iommu_ref_model/libiommu/src/iommu_command_queue.c
@@ -129,6 +129,10 @@ process_commands(
                     // the DID operand must not be wider than that supported by
                     // the ddtp.iommu_mode.
                     if ( command.iodir.dv != 1 ) goto command_illegal;
+                    // When DV operand is 1, the value of the DID operand must not
+                    // be wider than that supported by the ddtp.iommu_mode.
+                    if ( command.iodir.did & ~g_max_devid_mask )
+                        goto command_illegal;
                     // The PID operand of IODIR.INVAL_PDT must not be wider than
                     // the width supported by the IOMMU (see Section 5.3)
                     if ( g_reg_file.capabilities.pd20 == 0 && 

diff --git a/iommu_ref_model/test/test_app.c b/iommu_ref_model/test/test_app.c
@@ -2417,6 +2417,14 @@ main(void) {
     write_memory((char *)&cmd, ((cqb.ppn * PAGESIZE) | (cqh.index * 16)), 16);
     write_register(CQCSR_OFFSET, 4, cqcsr.raw);
 
+    // Invalidate PC - DID must not be too wide
+    g_max_devid_mask = 0x3F;
+    process_commands();
+    cqcsr.raw = read_register(CQCSR_OFFSET, 4);
+    fail_if( ( cqcsr.cmd_ill != 1 ) );
+    g_max_devid_mask = 0xFFFFFF;
+    write_register(CQCSR_OFFSET, 4, cqcsr.raw);
+
     // Process the fixed up command
     process_commands();