target/riscv: Stop caching writes to DPC #952
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Since DPC is WARL (same rules as MEPC according to the specification), it is possible that writes to it won't result in the exact value present. Therefore, writes to it shouldn't be cached, same as with other WARL registers. Change-Id: I818c0cef9727b999b7d84b19f9f42cd706c99d69 Signed-off-by: Marek Vrbka <[email protected]>
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JanMatCodasip
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Nov 3, 2023
timsifive
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Nov 3, 2023
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I believe that's right. And that's exactly what the code says on line 4980. https://github.com/riscv/riscv-openocd/pull/952/files#diff-b4aa16f9e42cb8f0934baa7c8e0ec9c70a369bef98b99b26ae2e896c8aa95d6aR4980 It is just not immediately apparent due to the diff shown being too short :-) |
timsifive
approved these changes
Nov 6, 2023
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Since DPC is WARL (same rules as MEPC according to the specification), it is possible that
writes to it won't result in the exact value present. Therefore, writes to it shouldn't be cached, same as with other WARL registers.
Change-Id: Ib7a4041bc2730c3cd40d5a4db8ba52a8e8788256