target/riscv: access registers via reg->type
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Please note: this PR cherry-picks https://review.openocd.org/c/openocd/+/8070 |
1) OpenOCD has the capability to 'force' a register read from the target. This functionality however silently breaks the register cache: During 'get_reg force' or 'reg <name> force', reg->type->get() is called which will silently overwrite dirty items in the register cache, causing a loss of unwritten register values. This patch fixes that by adding a flush callback for registers, and by using it when it is needed. 2) The register write commands did not have the 'force' flag; this was present for register read commands only. This patch adds it. 3) This patch also introduces the flush_reg_cache command. It flushes all registers and can optionally invalidates the register cache after the flush. For targets which implement the register cache should implement the flush() callback in struct reg_arch_type. This functionality is also useful for test purposes. Example: - In RISC-V, some registers are WARL (write any read legal) and this command allows to check this behavior. We plan to implement the corresponding callback in the RISC-V target. Change-Id: I9537a5f05b46330f70aad17f77b2b80dedad068a Signed-off-by: Marek Vrbka <[email protected]> Signed-off-by: Jan Matyas <[email protected]>
* `int riscv_reg_get()` and `int riscv_reg_set()` are implemented in
terms of `reg->type->get/set` instead of the other way around. This
makes it easier to support custom behavior for some registers.
* Cacheability is determined by `reg->type` instead of
`riscv_reg_impl_gdb_regno_cacheable()`.
* Issues with redirection of `priv` -> `dcsr` and `pc` -> `dpc` are
addressed at the "topmost" level.
- `priv` and `pc` are alvais invalid.
- Fixed some issues, e.g. the first `pc` write printed-out an
uninitialized value:
```
> reg pc 0
pc (/64): 0x000075da6b33db20
```
Change-Id: I514547f455d62b289fb5dee62753bf5d9aa3b8ae
Signed-off-by: Evgeniy Naydanov <[email protected]>
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int riscv_reg_get()andint riscv_reg_set()are implemented interms of
reg->type->get/setinstead of the other way around. Thismakes it easier to support custom behavior for some registers.
reg->typeinstead ofriscv_reg_impl_gdb_regno_cacheable().priv->dcsrandpc->dpcareaddressed at the "topmost" level.
privandpcare alvais invalid.pcwrite printed-out anuninitialized value: