clk: mediatek: add UART0 clock support

[ Upstream commit 804a892 ] Add MT6779 UART0 clock support. Fixes: 710774e ("clk: mediatek: Add MT6779 clock support") Signed-off-by: Wendell Lin <[email protected]> Signed-off-by: Hanks Chen <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> Signed-off-by: Sasha Levin <[email protected]>
raspberrypi · Oct 29, 2020 · a3de471 · a3de471
1 parent 4f621de
commit a3de471
Showing 1 changed file with 2 additions and 0 deletions.
diff --git a/drivers/clk/mediatek/clk-mt6779.c b/drivers/clk/mediatek/clk-mt6779.c
@@ -919,6 +919,8 @@ static const struct mtk_gate infra_clks[] = {
 		    "pwm_sel", 19),
 	GATE_INFRA0(CLK_INFRA_PWM, "infra_pwm",
 		    "pwm_sel", 21),
+	GATE_INFRA0(CLK_INFRA_UART0, "infra_uart0",
+		    "uart_sel", 22),
 	GATE_INFRA0(CLK_INFRA_UART1, "infra_uart1",
 		    "uart_sel", 23),
 	GATE_INFRA0(CLK_INFRA_UART2, "infra_uart2",