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1. DE0-Verilog-Processor DE0-Verilog-Processor Public

   Forked from oblivioncth/DE0-Verilog-Processor

   A fully functional 16-bit virtual processor (harvard architecture) created from scratch using Verliog, an Altera DE0, and peripheral board. The processor is paired with 256 KB of RAM and accepts as…

   Verilog

2. ramfile ramfile Public

   Forked from cassuto/ramfile

   Generic RAM blocks described in Verilog HDL for FPGA Verification.

   Verilog

3. 2-way-Set-Associative-Cache-Controller 2-way-Set-Associative-Cache-Controller Public

   Forked from prasadp4009/2-way-Set-Associative-Cache-Controller

   Synthesizable and Parameterized Cache Controller in Verilog

   Verilog

4. MIPS-Processor-in-Verilog MIPS-Processor-in-Verilog Public

   Forked from Caskman/MIPS-Processor-in-Verilog

   Processor repo

   Verilog

5. kivantium-old kivantium-old Public

   Forked from kivantium/kivantium-core

   A RISC-V based CPU in SystemVerilog

   C

6. UVM UVM Public

   Forked from mayurkubavat/UVM-Examples

   UVM examples and projects

   SystemVerilog 1