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In order to use the SYSTICK monotonic, we'll need to have a SYSTICK interrupt + ISR handler. This handler will need to execute once per tick rate (e.g. at 1KHz tick rate, ISR will run every 1ms).
This ISR can either be higher or lower priority to the DSP process:
If higher priority, the ISR must be short enough to not interrupt DSP process() timing requirements
If lower priority, the DSP process() routine must always be shorter than the tick period for all possible batch sizes
The current DSP process() shortest allowable time is with a batch size of 1 at the full 780KHz sample rate, which corresponds to ~1.28uS. This corresponds to roughly ~512 CPU cycles at 400MHz.
If we can show the SYSTICK ISR overhead will fit within that period, we can make the SYSTICK a higher priority. If not, we'll have to make the SYSTICK a lower priority and add a caveat that the process() routine must always be shorter than the timer tick rate.
I think trying to guarantee that the ISR will fit within those 512 clock cycles would be tricky, so it's likely the best path to set the SYSTICK rate to something decently long and add a compile-time check to ensure that the batch capture period is shorter than the systick duration
I made rtic-rs/dwt-systick-monotonic#6 and tested on fls (just for the RTIC monotonic, not the SystemTimer Clock for NAL etc).
But I think we should just use
systick-monotonic
at 1 kHz (which also works fine). wrappingmonotonics::now().ticks()
might be all we need forClock
.https://github.com/rtic-rs/systick-monotonic
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