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Propagate split dtype to join #817

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Apr 10, 2024
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8d31061
Ensure dtypes get used when joining typed registers.
fdmalone Mar 21, 2024
e97cff3
Fix tests.
fdmalone Mar 22, 2024
bd8027e
Update for black?
fdmalone Mar 22, 2024
b15ce91
Ensure dtypes get used when joining typed registers.
fdmalone Mar 21, 2024
a937349
Fix tests.
fdmalone Mar 22, 2024
dae08f0
Update for black?
fdmalone Mar 22, 2024
f3eed5e
Don't rely on soq reg.
fdmalone Mar 22, 2024
776ec28
WIP testing.
fdmalone Mar 22, 2024
60183cd
Add bloq autotesting + update report card.
fdmalone Mar 22, 2024
b4e28ea
Merge branch 'propagate_split_dtype_to_join' of github.com:fdmalone/Q…
fdmalone Mar 22, 2024
019812b
Fix interop.
fdmalone Mar 24, 2024
8b2b1b5
Better typed show_bloqs.
fdmalone Mar 24, 2024
08b514b
Fixes.
fdmalone Mar 25, 2024
f01af84
Fix lint errors.
fdmalone Mar 25, 2024
7b42be7
Merge branch 'main' into propagate_split_dtype_to_join
fdmalone Mar 25, 2024
b49171e
Fix formatting.
fdmalone Mar 25, 2024
5d1adec
Fix test failures.
fdmalone Mar 25, 2024
da2f1b7
Fix formatting.
fdmalone Mar 25, 2024
819f9df
Merge branch 'main' into propagate_split_dtype_to_join
fdmalone Mar 29, 2024
6d9ab70
Merge branch 'main' into propagate_split_dtype_to_join
fdmalone Apr 5, 2024
1080ea1
Clean cirq_bloq_interop typing.
fdmalone Apr 5, 2024
7d10c75
Remove prints.
fdmalone Apr 5, 2024
281dcf8
Safer casting.
fdmalone Apr 5, 2024
b620f4f
Safer checking.
fdmalone Apr 6, 2024
c52390b
Remove print.
fdmalone Apr 6, 2024
2de1b34
Format / lint.
fdmalone Apr 6, 2024
2c79572
Only cast Fxp.
fdmalone Apr 6, 2024
f78ce7a
Custom hash for _QReg for single-qubit lookup.
fdmalone Apr 8, 2024
31519a8
Address review comments.
fdmalone Apr 10, 2024
bbf40c3
Add assertion.
fdmalone Apr 10, 2024
a8cc8be
Move location of assert.
fdmalone Apr 10, 2024
5259aa9
Merge branch 'main' into propagate_split_dtype_to_join
fdmalone Apr 10, 2024
86d4429
Move assert back.
fdmalone Apr 10, 2024
5ba5cb7
Merge branch 'propagate_split_dtype_to_join' of github.com:fdmalone/Q…
fdmalone Apr 10, 2024
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2 changes: 1 addition & 1 deletion qualtran/bloqs/util_bloqs.py
Original file line number Diff line number Diff line change
Expand Up @@ -434,7 +434,7 @@ class Cast(Bloq):
)

def __attrs_post_init__(self):
if isinstance(self.inp_dtype.bitsize, int):
if isinstance(self.inp_dtype.num_qubits, int):
if self.inp_dtype.num_qubits != self.out_dtype.num_qubits:
raise ValueError("Casting only permitted between same sized registers.")

Expand Down
18 changes: 8 additions & 10 deletions qualtran/cirq_interop/_cirq_to_bloq.py
Original file line number Diff line number Diff line change
Expand Up @@ -34,7 +34,6 @@
QAny,
QBit,
QDType,
QFxp,
Register,
Side,
Signature,
Expand All @@ -46,6 +45,7 @@
get_named_qubits,
split_qubits,
)
from qualtran.bloqs.util_bloqs import Cast
from qualtran.cirq_interop._interop_qubit_manager import InteropQubitManager
from qualtran.cirq_interop.t_complexity_protocol import t_complexity, TComplexity
from qualtran.simulation.tensor._tensor_data_manipulation import (
Expand Down Expand Up @@ -251,7 +251,7 @@ def _ensure_in_reg_exists(
n_alloc = len(qubits_to_allocate)
qreg_to_qvar[
_QReg(qubits_to_allocate, dtype=QBit() if n_alloc == 1 else QAny(n_alloc))
] = bb.allocate(len(qubits_to_allocate))
] = bb.allocate(n_alloc)

if in_reg in qreg_to_qvar:
# This is the easy case when no split / joins are needed.
Expand All @@ -275,17 +275,15 @@ def _ensure_in_reg_exists(
for qreg, soq in new_qreg_to_qvar.items():
if len(in_reg_qubits) > 1 and qreg.qubits and qreg.qubits[0] in in_reg_qubits:
assert len(qreg.qubits) == 1, "Individual qubits should have been split by now."
# Need to split single-qubit Fxp registers which are ambiguous,
# these will be appropriately joined later.
if isinstance(qreg.dtype, QFxp):
soqs_to_join[qreg.qubits[0]] = bb.split(soq=soq)[0]
# Cast single bit registers to QBit to preserve signature of later join.
if not isinstance(qreg.dtype, QBit):
soqs_to_join[qreg.qubits[0]] = bb.add(Cast(qreg.dtype, QBit()), reg=soq)
else:
soqs_to_join[qreg.qubits[0]] = soq
elif len(in_reg_qubits) == 1 and qreg.qubits and qreg.qubits[0] in in_reg_qubits:
# Need to split single-qubit Fxp registers which are ambiguous,
# these will be appropriately joined later.
if isinstance(qreg.dtype, QFxp):
soqs_to_join[qreg.qubits[0]] = bb.split(soq=soq)[0]
# Cast single QBit registers to the appropriate single-bit register dtype.
if not isinstance(in_reg.dtype, QBit):
qreg_to_qvar[in_reg] = bb.add(Cast(QBit(), in_reg.dtype), reg=soq)
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else:
qreg_to_qvar[qreg] = soq
else:
Expand Down
17 changes: 13 additions & 4 deletions qualtran/testing.py
Original file line number Diff line number Diff line change
Expand Up @@ -552,7 +552,19 @@ def check_bloq_example_serialize(bloq_ex: BloqExample) -> Tuple[BloqCheckResult,


def assert_bloq_example_preserves_types(bloq_ex: BloqExample) -> Tuple[BloqCheckResult, str]:
""" """
"""Check a bloq example preserves types throughout its decomposition.

Args:
bloq_ex: The bloq example to test.

Returns:
None

Raises:
BloqCheckException if any assertions are violated. Will raise a failure
if loose type checking fails, and unverified if the stricter type checks
fail.
"""
bloq = bloq_ex.make()
# First check it's not atomic / doesn't decompose
try:
Expand Down Expand Up @@ -582,9 +594,6 @@ def assert_bloq_example_preserves_types(bloq_ex: BloqExample) -> Tuple[BloqCheck
def check_connections_preserve_preserves_types(bloq_ex: BloqExample) -> Tuple[BloqCheckResult, str]:
"""Check that the BloqExample has consistent typing.

This checks that the composite bloq's register dtypes are strictly the same, i.e.
no casting occurs.

Returns:
result: The `BloqCheckResult`.
msg: A message providing details from the check.
Expand Down
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