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Add explicit test for zero-size registers
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charlesyuan314 committed Jul 1, 2024
1 parent dee6b8f commit 7e18cfe
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Showing 2 changed files with 18 additions and 1 deletion.
2 changes: 1 addition & 1 deletion qualtran/_infra/registers.py
Original file line number Diff line number Diff line change
Expand Up @@ -151,7 +151,7 @@ def build(cls, **registers: Union[int, sympy.Expr]) -> 'Signature':
will be 0-dimensional and THRU.
"""
return cls(
Register(name=k, dtype=QBit() if v == 1 else QAny(v)) for k, v in registers.items() if v
Register(name=k, dtype=QBit() if v == 1 else QAny(v)) for k, v in registers.items()
)

@classmethod
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17 changes: 17 additions & 0 deletions qualtran/_infra/registers_test.py
Original file line number Diff line number Diff line change
Expand Up @@ -33,6 +33,17 @@ def test_register():
assert r == r.adjoint()


def test_zero_register():
r = Register("my_reg", QAny(0))
assert r.name == "my_reg"
assert r.bitsize == 0
assert r.shape == tuple()
assert r.side == Side.THRU
assert r.total_bits() == 0

assert r == r.adjoint()


def test_multidim_register():
r = Register("my_reg", QBit(), shape=(2, 3), side=Side.RIGHT)
idxs = list(r.all_idxs())
Expand Down Expand Up @@ -127,6 +138,12 @@ def test_signature_build():
sig2 = Signature.build(r1=5, r2=2)
assert sig1 == sig2
assert sig1.n_qubits() == 7

sig1 = Signature([Register("r1", QAny(0)), Register("r2", QAny(2))])
sig2 = Signature.build(r1=0, r2=2)
assert sig1 == sig2
assert sig1.n_qubits() == 2

sig1 = Signature([Register("r1", QInt(7)), Register("r2", QBit())])
sig2 = Signature.build_from_dtypes(r1=QInt(7), r2=QBit())
assert sig1 == sig2
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