Speed up 1Q/2Q RB

[itoko]

Summary

Improve the performance of transpiled circuit generation in 1Q/2Q StandardRB/InterleavedRB (about 10x speedup in 1Q SRB/IRB and 5x speedup in 2Q SRB/IRB in most cases).

Details and comments

This commit merges several commits developed in feature/rb_speedup branch, which includes the main PR #892 implementing the two main ideas below and two follow-up PRs #922 and #940 for improving the implementation.

• Custom transpilation (basis translation and qubit layouting without using transpile)
• Integer-based Clifford operations (storing lookup tables in npz format (sparse table for 2Q Clifford composition))

In total, this commit achieves the speedup without changing public APIs of StandardRB/InterleavedRB. It also includes other minor improvements such as

• Fix performance regression in 3 or more qubits RB (embedded at Refactor RB module for future extensions #898)
• Improve validation of interleave_element in InterleavedRB
• Restructure tests for RB module
• Remove the barriers in front of the first Cliffords in RB circuits

Note that this commit does not always achieve the speedup for 1Q/2Q RB. For example, if the backend does not support bi-directional two-qubit gate in the qubits for 2Q RB or if some custom transpile_options such as inst_map is supplied, it will fall back to the original slow path calling transpile. For benchmarking your own gate calibration, supply it via InstructionProperties.calibration in BackendV2 instead of inst_map in transpile_options (See this notebook for the details).

Co-authored-by: merav-aharoni [email protected]

[itoko]

Benchmark results comparing main and feature/rb_speedup branch:

Benchmark code:

num_lengths = 10
# run several experiments with changing max clifford length (max_length)
for max_length in [1000, 2000, 3000, 4000, 5000]:  # [100, 200, 300, 400, 500] for 2Q RBs
    exp = StandardRB(
        qubits=[2],  # for 1Q RBs ([2, 1] for 2Q RBs)
        lengths=np.arange(1, max_length, max_length // num_lengths),  # see below for examples
        backend=FakeManilaV2(),
        num_samples=3,
        full_sampling=False,
    )
    # measure the time to generate transpiled RB circuits
    exp._transpiled_circuits()

Table data (used to plot the above graph):
1Q SRB:

max_length	rb_speedup[s]	main[s]	main->rb_speedup
1000	0.752348	6.717184	0.112004
2000	1.297973	12.989921	0.099922
3000	1.917028	19.794178	0.096848
4000	2.591277	26.269336	0.098643
5000	3.257383	32.618234	0.099864

2Q SRB:

max_length	rb_speedup[s]	main[s]	main->rb_speedup
100	0.537246	1.976430	0.271826
200	0.606702	3.690494	0.164396
300	0.884264	5.088596	0.173774
400	1.145638	6.611528	0.173279
500	1.386664	8.179900	0.169521

1Q IRB:

max_length	rb_speedup[s]	main[s]	main->rb_speedup
1000	1.661791	18.873485	0.088049
2000	2.352290	37.004114	0.063568
3000	3.596937	56.356628	0.063825
4000	4.801674	79.195293	0.060631
5000	5.893142	96.097024	0.061325

2Q IRB:

max_length	rb_speedup[s]	main[s]	main->rb_speedup
100	1.014176	4.121180	0.246089
200	0.912129	7.153537	0.127507
300	1.316064	10.007865	0.131503
400	1.736773	13.106068	0.132517
500	2.094762	16.098833	0.130119

[ihincks]

All the pieces in this PR are making sense to me, and, IMO, it should be pretty close to merging. Nice work!

As a relatively new contributor to this repository, I have some lingering concerns about the direct use of private QuantumCircuit attributes in clifford_utils.py, but my understanding is that certain allowances are made for qiskit_experiments to break standard Python conventions in this regard due to performance requirements. I do, however, encourage everyone to take a last look at all the places, where, for instance, _data is directly modified so that we might check if it is actually much faster than the safer _append.

[ihincks]

Everything's looking great. I have one last comment.

[ihincks]

Thank you @itoko and @merav-aharoni for this fantastic PR!

[airwoodix]

@itoko while upgrading from 0.4.0 to 0.5.x, I noticed that, under default settings, this PR bypasses the transpilation settings set by the backend. While the speed benefits are clear, it makes it difficult for backend implementations to guarantee invariants after transpilation, since the fast-track transpiler is not pluggable and fully bypasses the regular transpiler.

Is there a mechanism in place one could use to register certain transpilation passes after applying _transpile_clifford_circuit? Thanks.

[itoko]

@airwoodix Excuse me, I've just noticed your comment. Unfortunately, upgraded RB experiments does not provide any simple way to tweak transpiled rb circuits without sacrificing speed. A workaround I can think of is subclassing, i.e. overriding _transpiled_circuits method in the subclass to run your own transpilation passes, e.g.

class MyRB(StandardRB):
    def _transpiled_circuits():
        new_circuits = super()._transpiled_circuits()
        new_circuits = my_pass_manager.run(new_circuits)
        return new_circuits