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Fixed kwargs not being expanded for actions on bit registers #2161

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merged 1 commit into from
Apr 13, 2024
Merged

Fixed kwargs not being expanded for actions on bit registers #2161

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5 changes: 3 additions & 2 deletions pymodbus/datastore/simulator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -435,7 +435,7 @@ class ModbusSimulatorContext(ModbusBaseSlaveContext):
"write": [ --> allow write, efault is ReadOnly
[5, 5] --> start, end bytes, repeated as needed
],
"bits": [ --> Define bits (1 register == 1 byte)
"bits": [ --> Define bits (1 register == 2 bytes)
[30, 31], --> start, end registers, repeated as needed
{"addr": [32, 34], "value": 0xF1}, --> with value
{"addr": [35, 36], "action": "increment"}, --> with action
Expand Down Expand Up @@ -602,8 +602,9 @@ def getValues(self, func_code, address, count=1):
for i in range(real_address, real_address + reg_count):
reg = self.registers[i]
if reg.action:
kwargs = reg.action_kwargs or {}
self.action_methods[reg.action](
self.registers, i, reg, reg.action_kwargs
self.registers, i, reg, **kwargs
)
self.registers[i].count_read += 1
while count and bit_index < 16:
Expand Down
14 changes: 12 additions & 2 deletions test/sub_server/test_simulator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -528,7 +528,12 @@ def test_simulator_action_increment(
exc_simulator.registers[30].value = regs[0]
exc_simulator.registers[31].value = regs[1]
for expect_value in expected:
regs = exc_simulator.getValues(FX_READ_REG, 30, reg_count)
if celltype != CellType.BITS:
regs = exc_simulator.getValues(FX_READ_REG, 30, reg_count)
else:
reg_bits = exc_simulator.getValues(FX_READ_BIT, 30 * 16, 16)
reg_value = sum([ bit * 2 ** i for i, bit in enumerate(reg_bits)])
regs = [reg_value]
if reg_count == 1:
assert expect_value == regs[0], f"type({celltype})"
else:
Expand Down Expand Up @@ -563,7 +568,12 @@ def test_simulator_action_random(self, celltype, minval, maxval):
is_int = celltype != CellType.FLOAT32
reg_count = 1 if celltype in (CellType.BITS, CellType.UINT16) else 2
for _i in range(100):
regs = exc_simulator.getValues(FX_READ_REG, 30, reg_count)
if celltype != CellType.BITS:
regs = exc_simulator.getValues(FX_READ_REG, 30, reg_count)
else:
reg_bits = exc_simulator.getValues(FX_READ_BIT, 30 * 16, 16)
reg_value = sum([ bit * 2 ** i for i, bit in enumerate(reg_bits)])
regs = [reg_value]
if reg_count == 1:
new_value = regs[0]
else:
Expand Down