mem_to_banks_detailed: Fix HideStrb alignment
#225
GitHub Actions / verible-verilog-lint
failed
Jul 11, 2024 in 0s
reviewdog [verible-verilog-lint] report
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Findings (2)
src/mem_to_banks_detailed.sv|159 col 101| Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
src/mem_to_banks_detailed.sv|160 col 101| Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
Filtered Findings (0)
Annotations
Check warning on line 159 in src/mem_to_banks_detailed.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_to_banks_detailed.sv#L159
Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]" location:{path:"./src/mem_to_banks_detailed.sv" range:{start:{line:159 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 160 in src/mem_to_banks_detailed.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] src/mem_to_banks_detailed.sv#L160
Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]" location:{path:"./src/mem_to_banks_detailed.sv" range:{start:{line:160 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
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