v1.29.0

1.29.0 - 2023-04-14

Added

• Add shift_reg_gated: Shift register with ICG for arbitrary types.

Changed

• CI: Run testbenches in test/ on internal gitlab mirror.
• fifo_tb: Add test for DEPTH not power of two.

Fixed

• clk_int_div: Allow configuration while clock is disabled.
• mem_to_banks: Cut possible timing loop for HideStrb feature.
• Improved tool compatibility (Verilator, Questasim, Synopsys).

v1.28.0

1.28.0 - 2022-12-15

Added

• Add clk_mux_glitch_free: A glitch-free clock multiplexer.

v1.27.1

1.27.1 - 2022-12-06

Fixed

• fall_through_register: Remove superfluous $size() call for tool compatibility

v1.27.0

1.27.0 - 2022-12-01

Added

• Add mem_to_banks: split memory access over multiple parallel banks. Moved from the AXI4+ATOP
axi_to_mem module.
• Add read: dummy module that prevents a signal from being removed during synthesis

Changed

• stream_fifo_optimal_wrap: Remove asserts
• fall_through_register: Update fifo to fifo_v3

Fixed

• FuseSoC: Add assertions.svh

v1.26.0

1.26.0 - 2022-08-26

Added

• Add stream_throttle: restricts the number of outstanding transfers in a stream.

Changed

• Allow out-of-bounds (i.e. '0) top end address in addr_map of addr_decode module for end of address space.
• Update CI.

v1.25.0

1.25.0 - 2022-08-10

Added

• Add addr_decode_napot: variant of addr_decode which uses a base address and mask instead of a start and end address.
• Add stream_fifo_optimal_wrap: instantiates a more optimal spill_register instead of a stream_fifo for depth == 2.

Changed

• Make stream_register truly stream by replacing internal FIFO with FFs.
• Avoid using $bits() call in id_queue's parameters.
• Remove cb_filter and cb_filter_pkg from from Vivado IP packager project sources due to compatibility issues.
• Use tc_clk_mux as glitch-free muxes in rstgen_bypass to avoid combinational glitches.
• Avoid program blocks in testbenches for simulator compatibility.

Fixed

• Update src_files.yml and common_cells.core

v1.24.1

1.24.1 - 2022-04-13

Fixed

• Fix typos in Bender.yml and src_files.yml

v1.24.0

1.24.0 - 2022-03-31

Added

• Add edge_propagator_ack: Edge/pulse propagator with sender-synchronous receive-acknowledge
  output. edge_propagator is now implemented by instantiating edge_propagator_ack.
• Add 4phase_cdc: A 4 phase handshaking CDC that allows glitch-free resetting (used internally in the new clearable CDC IPs).
• Add one-sided clearable and/or async resettable flavors of 2phase CDC (cdc_2phase_clearable) and gray-counting FIFO CDCs (cdc_fifo_gray_clearable).
• Add reset CDC controller cdc_reset_ctrl that supports reset/synchronous clear sequencing across clock domain crossings (used internally in clearable CDC IPs).
• Add clk_int_div arbitrary integer clock divider with at-runtime
  configurable divider selection and glitch-free, 50%duty cycle output clock.
• Add an assertion to the lzc to verify parameters.

Fixed

• Correct reset polarity in assertions in isochronous_4phase_handshake and isochronous_spill_register
• Fix compatibility of sub_per_hash constructs with Verilator

Changed

• Add dont_touch and async_reg attribute to FFs in sync cell.
• Improved reset behavior documentation (in module header) of existing CDC IPs.
• Deprecated flawed clk_div module and add elaboration warning message that
  will be shown for existing designs (can be disabled with optional
  instantiation parameter).
• Add optional Seed parameter to stream_delay module
• Update tech_cells_generic to 0.2.9

v1.23.0

1.23.0 - 2021-09-05

Added

• Add cc_onehot
• isochronous_4phase_handshake: Isochronous clock domain crossing cutting all paths using a 4-phase handshake.
• Changed isochronous_spill_register_tb to isochronous_crossing_tb also covering the isochronous_4phase_handshake
  module.
• Make reset value of sync module parameterizable.

Changed

• id_queue: Allow simultaneous input and output requests in FULL_BW mode

v1.22.1

1.22.1 - 2021-06-14

Fixed

• Remove breaking change of spill_register