v1.22.0

1.22.0 - 2021-06-09

Added

• Add spill_register_flushable

Changed

• registers.svh: Merge explicit and implicit register variants into `FF and `FFL macros
• rr_arb_tree: Allow flushing locked decision
• Improved verific compatibility

v1.21.0

1.21.0 - 2021-01-28

Changed

• Remove timeprecision/timeunit arguments
• Update common_verification to 0.2.0
• Update tech_cells_generic to 0.2.3

v1.20.1

Changed

• id_queue: Replace default or reset value of signals that were assigned 'x with '0.
• id_queue: Use cf_math_pkg::idx_width() for computation of localparams.

Fixed

• Add XSIM define guard for statements incompatible with xsim.

v1.20.0

Added

• assertions: Assertion include header with macros (from lowrisc)

Changed

• sram.sv: Deprecated as it has been moved to tech_cells_generic

Fixed

• stream_register: Fix DATA_WIDTH of instantiated FIFO.
• stream_xbar: Add missing argument in assertion error string.
• Lint style fixes
• stream_omega: Fix parse issue with verible.
• src_files.yml: Fix compile order and missing modules.

v1.19.0

Added

• stream_to_mem: Allows to use memories with flow control (req/gnt) for requests but
  without flow control for output data to be used in streams.
• isochronous_spill_register: Isochronous clock domain crossing cutting all paths.
• rr_arb_tree_tb: Systemverilog testbench for rr_arb_tree, which checks for fair throughput.
• cf_math_pkg::idx_width: Constant function for defining the binary representation width
  of an index signal.

Changed

• addr_decode: Use cf_math_pkg::idx_width for computing the index width, inline documentation.
• lzc: Use cf_math_pkg::idx_width for computing the index width, inline documentation.
• Bender: Change levels of modules affected by depending on cf_math_pkg::idx_width().
• stream_xbar: Fully connected stream bassed interconnect with variable number of inputs and outputs.
• stream_xbar: Fully connected stream-bassed interconnect with a variable number of inputs and outputs.

Fixed

• Improve tool compatibility.
• rr_arb_tree: Properly degenerate rr_i and idx_o signals.
• rr_arb_tree: Add parameter FairArb to distribute throughput of input requests evenly when
  not all inputs have requests active.
• stream_demux: Properly degenerate inp_sel_i signal.

v1.18.0

Added

• stream_fork_dynamic: Wrapper around stream_fork for partial forking.
• stream_join: Join multiple Ready/Valid handshakes to one common handshake.
• SECDED (Single Error Correction, Double Error Detection) encoder and decoder
• SECDED Verilator-based testbench
• Travis build for SECDED module

v1.17.0

Added

• stream_fifo: Ready/Valid handshake wrapper around fifo_v3

v1.16.4

Fixed

id_queue: Fix generation of head_tail_q registers

There are HT_CAPACITY registers behind the head_tail_q signal, and
the value of HT_CAPACITY need not necessarily be the same as
CAPACITY.

1.16.0 - 2020-01-13

• Handle degenerated onehot_to_bin with ONEHOT_WIDTH == 1
• Handle degenerated id_queue with CAPACITY == 1 or HT_CAPACITY == 1
• Fix cdc_fifo_gray to be a safe clock domain crossing (CDC)

1.15.0 - 2019-12-09

1.15.0 - 2019-12-09

Added

• Added address map decoder module

Fixed

• Handle degenerated lzc with WIDTH == 1