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Add credit_counter
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Co-authored-by: Paul Scheffler <[email protected]>
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micprog and paulsc96 committed Jul 17, 2024
1 parent be3866e commit d99b266
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1 change: 1 addition & 0 deletions Bender.yml
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Expand Up @@ -32,6 +32,7 @@ sources:
- src/cdc_reset_ctrlr_pkg.sv
- src/cf_math_pkg.sv
- src/clk_int_div.sv
- src/credit_counter.sv
- src/delta_counter.sv
- src/ecc_pkg.sv
- src/edge_propagator_tx.sv
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4 changes: 4 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -4,6 +4,10 @@ All notable changes to this project will be documented in this file.
The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).

## Unreleased
### Added
- `credit_counter`: Add up/down counter for credit.

## 1.36.0 - 2024-07-08
### Fixed
- `registers`: Fix else statement in FFARNC macro.
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1 change: 1 addition & 0 deletions README.md
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Expand Up @@ -55,6 +55,7 @@ Please note that cells with status *deprecated* are not to be used for new desig
| Name | Description | Status | Superseded By |
| ------------------- | ----------------------------------------------------------------- | ------------ | ------------- |
| `counter` | Generic up/down counter with overflow detection | active | |
| `credit_counter` | Up/down counter for credit | active | |
| `delta_counter` | Up/down counter with variable delta and overflow detection | active | |
| `generic_LFSR_8bit` | 8-bit linear feedback shift register (LFSR) | *deprecated* | `lfsr_8bit` |
| `lfsr_8bit` | 8-bit linear feedback shift register (LFSR) | active | |
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1 change: 1 addition & 0 deletions common_cells.core
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Expand Up @@ -16,6 +16,7 @@ filesets:
- src/cc_onehot.sv
- src/cf_math_pkg.sv
- src/clk_int_div.sv
- src/credit_counter.sv
- src/delta_counter.sv
- src/ecc_pkg.sv
- src/edge_propagator_tx.sv
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57 changes: 57 additions & 0 deletions src/credit_counter.sv
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// Copyright 2020 ETH Zurich and University of Bologna.
// Solderpad Hardware License, Version 0.51, see LICENSE for details.
// SPDX-License-Identifier: SHL-0.51

// Author: Fabian Schuiki <[email protected]>
// Author: Paul Scheffler <[email protected]>

`include "common_cells/registers.svh"
`include "common_cells/assertions.svh"

module credit_counter #(
parameter int unsigned NumCredits = 0,
/// Whether credit is full or empty on reset
parameter bit InitCreditEmpty = 1'b0,
/// Derived parameters *Do not override*
parameter int unsigned InitNumCredits = InitCreditEmpty ? '0 : NumCredits,
parameter type credit_cnt_t = logic [$clog2(NumCredits):0]
) (
input logic clk_i,
input logic rst_ni,

output credit_cnt_t credit_o,

input logic credit_give_i,
input logic credit_take_i,
input logic credit_init_i, // Reinitialize (soft-reset) credit; takes priority

output logic credit_left_o,
output logic credit_crit_o, // Giving one more credit will fill the credits
output logic credit_full_o
);

credit_cnt_t credit_d, credit_q;
logic increment, decrement;

assign decrement = credit_take_i & ~credit_give_i;
assign increment = ~credit_take_i & credit_give_i;

always_comb begin
credit_d = credit_q;
if (decrement) credit_d = credit_q - 1;
else if (increment) credit_d = credit_q + 1;
end

logic credit_load;
assign credit_load = 1'b1;
`FFLARNC(credit_q, credit_d, credit_load, credit_init_i, InitNumCredits, clk_i, rst_ni)

assign credit_o = credit_q;
assign credit_left_o = (credit_q != '0);
assign credit_crit_o = (credit_q == NumCredits-1);
assign credit_full_o = (credit_q == NumCredits);

`ASSERT_NEVER(CreditUnderflow, credit_o == '0 && decrement)
`ASSERT_NEVER(CreditOverflow, credit_o == NumCredits && increment)

endmodule
1 change: 1 addition & 0 deletions src_files.yml
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Expand Up @@ -11,6 +11,7 @@ common_cells_all:
- src/cc_onehot.sv
- src/cf_math_pkg.sv
- src/clk_int_div.sv
- src/credit_counter.sv
- src/delta_counter.sv
- src/ecc_pkg.sv
- src/edge_propagator_tx.sv
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