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pulp-platform / common_cells Public

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renamed translate_off to `ifndef SYNTHESIS #182

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renamed translate_off to `ifndef SYNTHESIS

renamed translate_off to `ifndef SYNTHESIS #182

Summary
Jobs
- Verilog Sources
- verible-verilog-lint
Run details
- Usage
- Workflow file

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Run time

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Job	Run time
Verilog Sources	37s
	37s

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