[HW]: Add mem_multibanked_pwrgate for correct power management #336
Lore0599Annotations
31 warnings
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L22:
src/mem_multibank_pwrgate.sv#L22
Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L23:
src/mem_multibank_pwrgate.sv#L23
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L24:
src/mem_multibank_pwrgate.sv#L24
Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L25:
src/mem_multibank_pwrgate.sv#L25
Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L26:
src/mem_multibank_pwrgate.sv#L26
Line length exceeds max: 100; is: 124 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L27:
src/mem_multibank_pwrgate.sv#L27
Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L28:
src/mem_multibank_pwrgate.sv#L28
Explicitly define a storage type for every parameter and localparam, (SimInit). [Style: constants] [explicit-parameter-storage-type]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L28:
src/mem_multibank_pwrgate.sv#L28
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L29:
src/mem_multibank_pwrgate.sv#L29
Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L30:
src/mem_multibank_pwrgate.sv#L30
Explicitly define a storage type for every parameter and localparam, (ImplKey). [Style: constants] [explicit-parameter-storage-type]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L30:
src/mem_multibank_pwrgate.sv#L30
Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L135:
src/mem_multibank_pwrgate.sv#L135
Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L138:
src/mem_multibank_pwrgate.sv#L138
Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L148:
src/mem_multibank_pwrgate.sv#L148
All generate block statements must have a label [Style: generate-statements] [generate-label]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L153:
src/mem_multibank_pwrgate.sv#L153
Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L22:
src/mem_multibank_pwrgate.sv#L22
Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L23:
src/mem_multibank_pwrgate.sv#L23
Line length exceeds max: 100; is: 102 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L24:
src/mem_multibank_pwrgate.sv#L24
Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L25:
src/mem_multibank_pwrgate.sv#L25
Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L26:
src/mem_multibank_pwrgate.sv#L26
Line length exceeds max: 100; is: 124 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L27:
src/mem_multibank_pwrgate.sv#L27
Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L28:
src/mem_multibank_pwrgate.sv#L28
Explicitly define a storage type for every parameter and localparam, (SimInit). [Style: constants] [explicit-parameter-storage-type]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L28:
src/mem_multibank_pwrgate.sv#L28
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L29:
src/mem_multibank_pwrgate.sv#L29
Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L30:
src/mem_multibank_pwrgate.sv#L30
Explicitly define a storage type for every parameter and localparam, (ImplKey). [Style: constants] [explicit-parameter-storage-type]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L30:
src/mem_multibank_pwrgate.sv#L30
Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L135:
src/mem_multibank_pwrgate.sv#L135
Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L138:
src/mem_multibank_pwrgate.sv#L138
Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L148:
src/mem_multibank_pwrgate.sv#L148
All generate block statements must have a label [Style: generate-statements] [generate-label]
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[verible-verilog-lint] src/mem_multibank_pwrgate.sv#L153:
src/mem_multibank_pwrgate.sv#L153
Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]
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gitlab-ci
The following actions use a deprecated Node.js version and will be forced to run on node20: actions/checkout@v3, actions/setup-python@v4. For more info: https://github.blog/changelog/2024-03-07-github-actions-all-actions-will-run-on-node20-instead-of-node16-by-default/
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