Skip to content

Replace all asserts & assumes with macros from assertions.svh #267

Replace all asserts & assumes with macros from assertions.svh

Replace all asserts & assumes with macros from assertions.svh #267

Re-run triggered September 30, 2024 09:59
Status Success
Total duration 54s
Artifacts 1

lint.yml

on: pull_request
Verilog Sources
41s
Verilog Sources
Fit to window
Zoom out
Zoom in

Annotations

1 warning
Verilog Sources
The following actions use a deprecated Node.js version and will be forced to run on node20: actions/checkout@v3. For more info: https://github.blog/changelog/2024-03-07-github-actions-all-actions-will-run-on-node20-instead-of-node16-by-default/

Artifacts

Produced during runtime
Name Size
verible-linter
164 Bytes