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Fix L0 testbench
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micprog committed Apr 30, 2024
1 parent 0612029 commit 306bc87
Showing 1 changed file with 23 additions and 9 deletions.
32 changes: 23 additions & 9 deletions test/snitch_icache_l0_tb.sv
Original file line number Diff line number Diff line change
Expand Up @@ -87,6 +87,7 @@ module snitch_icache_l0_tb #(
FETCH_DW: FETCH_DW,
FILL_AW: FILL_AW,
FILL_DW: FILL_DW,
L1_DATA_PARITY_BITS: 0,
L1_TAG_SCM: 1'b0,
EARLY_LATCH: EARLY_LATCH,
BUFFER_LOOKUP: BUFFER_LOOKUP,
Expand All @@ -107,8 +108,7 @@ module snitch_icache_l0_tb #(
PENDING_IW: $clog2(2)
};

localparam int unsigned IdWidthReq = $clog2(NR_FETCH_PORTS) + 1;
localparam int unsigned IdWidthResp = 2*NR_FETCH_PORTS;
localparam int unsigned IdWidth = 2*NR_FETCH_PORTS;

logic clk, rst;
logic dut_flush_valid;
Expand All @@ -121,12 +121,12 @@ module snitch_icache_l0_tb #(
typedef struct packed {
logic [LINE_WIDTH-1:0] data;
logic error;
logic [IdWidthResp-1:0] id;
logic [IdWidth-1:0] id;
} dut_in_t;

typedef struct packed {
addr_t addr;
logic [IdWidthReq-1:0] id;
logic [IdWidth-1:0] id;
} dut_out_t;

typedef stream_test::stream_driver #(
Expand Down Expand Up @@ -285,22 +285,36 @@ module snitch_icache_l0_tb #(
`ASSERT(RequestProgress, dut_valid |-> ##[0:RequestTimeout] dut_ready, clk, rst)

// Response Drivers
mailbox #(dut_out_t) addr_mbx [2];
mailbox #(dut_out_t) addr_mbx [IdWidth];
semaphore response_lock = new (1);

function logic [$clog2(IdWidth)-1:0] onehot2bin (input logic [IdWidth-1:0] onehot);

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GitHub Actions / verible-verilog-lint

[verible-verilog-lint] test/snitch_icache_l0_tb.sv#L291

Explicitly define static or automatic lifetime for non-class functions [Style: function-task-explicit-lifetime] [explicit-function-lifetime]
Raw output
message:"Explicitly define static or automatic lifetime for non-class functions [Style: function-task-explicit-lifetime] [explicit-function-lifetime]"  location:{path:"./test/snitch_icache_l0_tb.sv"  range:{start:{line:291  column:40}}}  severity:WARNING  source:{name:"verible-verilog-lint"  url:"https://github.com/chipsalliance/verible"}
logic [$clog2(IdWidth)-1:0] bin;
for (int i = 0; i < IdWidth; i++) begin
logic [IdWidth-1:0] tmp_mask;
for (int j = 0; j < IdWidth; j++) begin
logic [IdWidth-1:0] tmp_i;
tmp_i = j;
tmp_mask[j] = tmp_i[i];
end
bin[i] = |(tmp_mask & onehot);
end
return bin;
endfunction

initial begin
automatic int unsigned stall_cycles;
automatic dut_out_t dut_out;
for (int i = 0; i < 2**IdWidthReq; i++)
automatic dut_out_t dut_out_loc;
for (int i = 0; i < IdWidth; i++)
addr_mbx [i] = new();
out_driver.reset_out();
@(negedge rst);
repeat (5) @(posedge clk);
forever begin
stall_cycles = $urandom_range(0, 5);
repeat (stall_cycles) @(posedge clk);
out_driver.recv(dut_out);
addr_mbx[dut_out.id].put(dut_out);
out_driver.recv(dut_out_loc);
addr_mbx[onehot2bin(dut_out_loc.id)].put(dut_out_loc);
// $info("Requesting from Address: %h, ID: %d", dut_out.addr, dut_out.id);
end
end
Expand Down

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