Merge pull request #7 from pulp-platform/pr/basictouchup

Add Linting CI, first basic test

.github/workflows/lint.yml

@@ -26,6 +26,7 @@ jobs:
           (Solderpad Hardware License, Version 0.51|Licensed under the Apache License, Version 2.0), see LICENSE for details.
           SPDX-License-Identifier: (SHL-0.51|Apache-2.0)
         exclude_paths: |
+          targets/**/include/regs/*
           scripts/run_clang_format.py
 
   lint-cxx:

CMakeLists.txt

@@ -11,9 +11,16 @@ set(CMAKE_C_STANDARD 99)
 # SCHEREMO: Needed to skip compiler test, which doesn't support baremetal targets
 set(CMAKE_C_COMPILER_WORKS 1)
 
+# SCHEREMO: Help most IDE's LSPs find definitions
+set(CMAKE_EXPORT_COMPILE_COMMANDS 1)
+
 # SCHEREMO: This toolchain file is only used for test compilation!
 set(CMAKE_TOOLCHAIN_FILE cmake/toolchain_gcc.cmake)
 
+set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib)
+set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib)
+set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin)
+
 project(chimera-sdk LANGUAGES C ASM)
 
 include(${CMAKE_CURRENT_LIST_DIR}/cmake/Utils.cmake)

cmake/Utils.cmake

@@ -17,3 +17,15 @@ macro(add_chimera_test name)
   add_chimera_executable(${ARGV})
   add_test(NAME ${name} COMMAND ${name})
 endmacro()
+
+macro(add_target_source name)
+  if(NOT ${name} IN_LIST AVAILABLE_TARGETS)
+    message(FATAL_ERROR "Invalid value for TARGET_PLATFORM: Got ${TARGET_PLATFORM}")
+  endif()
+
+  if(EXISTS ${CMAKE_CURRENT_LIST_DIR}/${name})
+    add_subdirectory(${CMAKE_CURRENT_LIST_DIR}/${name})
+  else()
+    message(WARNING "Path ${CMAKE_CURRENT_LIST_DIR}/${name} does not exist")
+  endif()
+endmacro()

targets/CMakeLists.txt

@@ -5,16 +5,10 @@
 # Moritz Scherer <[email protected]>
 
 set(AVAILABLE_TARGETS
-  "Cheshire"
+  "chimera-open"
   CACHE STRING "Available Targets"
 )
 
 get_property(OPT_STRINGS CACHE OPT PROPERTY STRINGS)
 
-if(NOT TARGET_PLATFORM IN_LIST AVAILABLE_TARGETS)
-  message(FATAL_ERROR "Wrong value for TARGET_PLATFORM: Got ${TARGET_PLATFORM}")
-endif()
-
-if (TARGET_PLATFORM STREQUAL "Cheshire")
-  add_subdirectory(cheshire)
-endif()
+add_target_source(${TARGET_PLATFORM})

targets/cheshire/CMakeLists.txt → targets/chimera-open/CMakeLists.txt

@@ -5,14 +5,23 @@
 # Moritz Scherer <[email protected]>
 
 file(GLOB_RECURSE ASM_SOURCES
-  "src/crt0.S"
+  "src/runtime/crt0.S"
 )
+file(GLOB_RECURSE C_SOURCES
+  "src/*.c"
+)
+
 set_property(SOURCE ${ASM_SOURCES} PROPERTY LANGUAGE ASM)
-add_library(runtime OBJECT ${ASM_SOURCES})
+add_library(runtime OBJECT ${ASM_SOURCES} ${C_SOURCES})
 
 set(ISA rv32imc)
 set(ABI ilp32)
 
+target_include_directories(runtime
+  PUBLIC
+  ${CMAKE_CURRENT_LIST_DIR}/include
+)
+
 target_compile_options(runtime
   PUBLIC
   -march=${ISA}

targets/cheshire/common.ldh → targets/chimera-open/common.ldh

@@ -28,7 +28,7 @@ SECTIONS {
   /* Global and stack pointer */
   /* By default, keep the calling context (boot ROM) stack pointer */
   __global_pointer$ = ADDR(.misc) + SIZEOF(.misc) / 2;
-  __stack_pointer$  = 0;
+  __stack_pointer$  = ORIGIN(memisl) + LENGTH(memisl);
 
   /* Further addresses */
   __base_dma      = 0x01000000;

targets/chimera-open/include/regs/soc_ctrl.h

@@ -0,0 +1,104 @@
+// Generated register defines for chimera
+
+// Copyright information found in source file:
+// Copyright 2024 ETH Zurich and University of Bologna.
+
+// Licensing information found in source file:
+//
+// SPDX-License-Identifier: SHL-0.51
+
+#ifndef _CHIMERA_REG_DEFS_
+#define _CHIMERA_REG_DEFS_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+// Register width
+#define CHIMERA_PARAM_REG_WIDTH 32
+
+// Set boot address for all snitch cores
+#define CHIMERA_SNITCH_BOOT_ADDR_REG_OFFSET 0x0
+
+// Set interrupt handler address for all snitch cores
+#define CHIMERA_SNITCH_INTR_HANDLER_ADDR_REG_OFFSET 0x4
+
+// Register to store return value of Snitch cluster 0
+#define CHIMERA_SNITCH_CLUSTER_0_RETURN_REG_OFFSET 0x8
+
+// Register to store return value of Snitch cluster 1
+#define CHIMERA_SNITCH_CLUSTER_1_RETURN_REG_OFFSET 0xc
+
+// Register to store return value of Snitch cluster 2
+#define CHIMERA_SNITCH_CLUSTER_2_RETURN_REG_OFFSET 0x10
+
+// Register to store return value of Snitch cluster 3
+#define CHIMERA_SNITCH_CLUSTER_3_RETURN_REG_OFFSET 0x14
+
+// Register to store return value of Snitch cluster 4
+#define CHIMERA_SNITCH_CLUSTER_4_RETURN_REG_OFFSET 0x18
+
+// Enable clock gate for cluster 0
+#define CHIMERA_CLUSTER_0_CLK_GATE_EN_REG_OFFSET 0x1c
+#define CHIMERA_CLUSTER_0_CLK_GATE_EN_CLUSTER_0_CLK_GATE_EN_BIT 0
+
+// Enable clock gate for cluster 1
+#define CHIMERA_CLUSTER_1_CLK_GATE_EN_REG_OFFSET 0x20
+#define CHIMERA_CLUSTER_1_CLK_GATE_EN_CLUSTER_1_CLK_GATE_EN_BIT 0
+
+// Enable clock gate for cluster 2
+#define CHIMERA_CLUSTER_2_CLK_GATE_EN_REG_OFFSET 0x24
+#define CHIMERA_CLUSTER_2_CLK_GATE_EN_CLUSTER_2_CLK_GATE_EN_BIT 0
+
+// Enable clock gate for cluster 3
+#define CHIMERA_CLUSTER_3_CLK_GATE_EN_REG_OFFSET 0x28
+#define CHIMERA_CLUSTER_3_CLK_GATE_EN_CLUSTER_3_CLK_GATE_EN_BIT 0
+
+// Enable clock gate for cluster 4
+#define CHIMERA_CLUSTER_4_CLK_GATE_EN_REG_OFFSET 0x2c
+#define CHIMERA_CLUSTER_4_CLK_GATE_EN_CLUSTER_4_CLK_GATE_EN_BIT 0
+
+// Bypass cluster to mem wide connection for cluster 0
+#define CHIMERA_WIDE_MEM_CLUSTER_0_BYPASS_REG_OFFSET 0x30
+#define CHIMERA_WIDE_MEM_CLUSTER_0_BYPASS_WIDE_MEM_CLUSTER_0_BYPASS_BIT 0
+
+// Bypass cluster to mem wide connection for cluster 1
+#define CHIMERA_WIDE_MEM_CLUSTER_1_BYPASS_REG_OFFSET 0x34
+#define CHIMERA_WIDE_MEM_CLUSTER_1_BYPASS_WIDE_MEM_CLUSTER_1_BYPASS_BIT 0
+
+// Bypass cluster to mem wide connection for cluster 2
+#define CHIMERA_WIDE_MEM_CLUSTER_2_BYPASS_REG_OFFSET 0x38
+#define CHIMERA_WIDE_MEM_CLUSTER_2_BYPASS_WIDE_MEM_CLUSTER_2_BYPASS_BIT 0
+
+// Bypass cluster to mem wide connection for cluster 3
+#define CHIMERA_WIDE_MEM_CLUSTER_3_BYPASS_REG_OFFSET 0x3c
+#define CHIMERA_WIDE_MEM_CLUSTER_3_BYPASS_WIDE_MEM_CLUSTER_3_BYPASS_BIT 0
+
+// Bypass cluster to mem wide connection for cluster 4
+#define CHIMERA_WIDE_MEM_CLUSTER_4_BYPASS_REG_OFFSET 0x40
+#define CHIMERA_WIDE_MEM_CLUSTER_4_BYPASS_WIDE_MEM_CLUSTER_4_BYPASS_BIT 0
+
+// Register to identify when cluster 0 is busy
+#define CHIMERA_CLUSTER_0_BUSY_REG_OFFSET 0x44
+#define CHIMERA_CLUSTER_0_BUSY_CLUSTER_0_BUSY_BIT 0
+
+// Register to identify when cluster 1 is busy
+#define CHIMERA_CLUSTER_1_BUSY_REG_OFFSET 0x48
+#define CHIMERA_CLUSTER_1_BUSY_CLUSTER_1_BUSY_BIT 0
+
+// Register to identify when cluster 2 is busy
+#define CHIMERA_CLUSTER_2_BUSY_REG_OFFSET 0x4c
+#define CHIMERA_CLUSTER_2_BUSY_CLUSTER_2_BUSY_BIT 0
+
+// Register to identify when cluster 3 is busy
+#define CHIMERA_CLUSTER_3_BUSY_REG_OFFSET 0x50
+#define CHIMERA_CLUSTER_3_BUSY_CLUSTER_3_BUSY_BIT 0
+
+// Register to identify when cluster 4 is busy
+#define CHIMERA_CLUSTER_4_BUSY_REG_OFFSET 0x54
+#define CHIMERA_CLUSTER_4_BUSY_CLUSTER_4_BUSY_BIT 0
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+#endif // _CHIMERA_REG_DEFS_
+// End generated register defines for chimera

targets/chimera-open/include/soc_addr_map.h

@@ -0,0 +1,35 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Moritz Scherer <[email protected]>
+
+#ifndef _SOC_ADDR_MAP_INCLUDE_GUARD_
+#define _SOC_ADDR_MAP_INCLUDE_GUARD_
+
+#include <stdint.h>
+
+#define CLINT_CTRL_BASE 0x02040000
+
+#define SOC_CTRL_BASE 0x30001000
+
+#define CLUSTER_0_BASE 0x40000000
+#define CLUSTER_1_BASE 0x40200000
+#define CLUSTER_2_BASE 0x40400000
+#define CLUSTER_3_BASE 0x40600000
+#define CLUSTER_4_BASE 0x40800000
+
+#define CLUSTER_0_NUMCORES 9
+#define CLUSTER_1_NUMCORES 9
+#define CLUSTER_2_NUMCORES 9
+#define CLUSTER_3_NUMCORES 9
+#define CLUSTER_4_NUMCORES 9
+
+static uint8_t _chimera_numCores[] = {CLUSTER_0_NUMCORES, CLUSTER_1_NUMCORES, CLUSTER_2_NUMCORES,
+                                      CLUSTER_3_NUMCORES, CLUSTER_4_NUMCORES};
+#define _chimera_numClusters 5
+
+#define CHIMERA_PADFRAME_BASE_ADDRESS 0x30002000
+#define FLL_BASE_ADDR 0x30003000
+
+#endif

targets/chimera-open/include/soc_ctrl.h

@@ -0,0 +1,17 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Moritz Scherer <[email protected]>
+
+#ifndef _OFFLOAD_INCLUDE_GUARD_
+#define _OFFLOAD_INCLUDE_GUARD_
+
+#include <stdint.h>
+
+void setupInterruptHandler(void *handler);
+void offloadToCluster(void *function, uint8_t clusterId);
+void waitClusterBusy(uint8_t clusterId);
+uint32_t waitForCluster(uint8_t clusterId);
+
+#endif

targets/chimera-open/src/soc_ctrl.c

@@ -0,0 +1,91 @@
+// Copyright 2024 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Moritz Scherer <[email protected]>
+
+#include "regs/soc_ctrl.h"
+#include "soc_addr_map.h"
+#include "soc_ctrl.h"
+#include <stdint.h>
+
+void setupInterruptHandler(void *handler) {
+    volatile void **snitchTrapHandlerAddr =
+        (volatile void **)(SOC_CTRL_BASE + CHIMERA_SNITCH_INTR_HANDLER_ADDR_REG_OFFSET);
+
+    *snitchTrapHandlerAddr = handler;
+}
+
+void waitClusterBusy(uint8_t clusterId) {
+    volatile int32_t *busy_ptr;
+
+    if (clusterId == 0) {
+        busy_ptr = (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_0_BUSY_REG_OFFSET);
+    } else if (clusterId == 1) {
+        busy_ptr = (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_1_BUSY_REG_OFFSET);
+    } else if (clusterId == 2) {
+        busy_ptr = (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_2_BUSY_REG_OFFSET);
+    } else if (clusterId == 3) {
+        busy_ptr = (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_3_BUSY_REG_OFFSET);
+    } else if (clusterId == 4) {
+        busy_ptr = (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_CLUSTER_4_BUSY_REG_OFFSET);
+    }
+
+    while (*busy_ptr == 1) {
+    }
+    // TODO: temporary race condition fix
+    for (int i = 0; i < 1000; i++) {
+        // NOP
+        asm volatile("addi x0, x0, 0\n" :::);
+    }
+
+    return;
+}
+
+/* Offloads a void function pointer to the specified cluster's core 0 */
+void offloadToCluster(void *function, uint8_t clusterId) {
+
+    volatile void **snitchBootAddr =
+        (volatile void **)(SOC_CTRL_BASE + CHIMERA_SNITCH_BOOT_ADDR_REG_OFFSET);
+
+    *snitchBootAddr = function;
+
+    uint32_t hartId = 1;
+    for (uint32_t i = 0; i < clusterId; i++) {
+        hartId += _chimera_numCores[i];
+    }
+
+    volatile uint32_t *interruptTarget = ((uint32_t *)CLINT_CTRL_BASE) + hartId;
+    waitClusterBusy(clusterId);
+    *interruptTarget = 1;
+}
+
+/* Busy waits for the return of a cluster, clears the return register, and
+ * returns the return value */
+uint32_t waitForCluster(uint8_t clusterId) {
+    volatile int32_t *snitchReturnAddr;
+    if (clusterId == 0) {
+        snitchReturnAddr =
+            (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_0_RETURN_REG_OFFSET);
+    } else if (clusterId == 1) {
+        snitchReturnAddr =
+            (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_1_RETURN_REG_OFFSET);
+    } else if (clusterId == 2) {
+        snitchReturnAddr =
+            (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_2_RETURN_REG_OFFSET);
+    } else if (clusterId == 3) {
+        snitchReturnAddr =
+            (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_3_RETURN_REG_OFFSET);
+    } else if (clusterId == 4) {
+        snitchReturnAddr =
+            (volatile int32_t *)(SOC_CTRL_BASE + CHIMERA_SNITCH_CLUSTER_4_RETURN_REG_OFFSET);
+    }
+
+    while (*snitchReturnAddr == 0) {
+    }
+
+    uint32_t retVal = *snitchReturnAddr;
+    *snitchReturnAddr = 0;
+
+    return retVal;
+}

tests/CMakeLists.txt

@@ -4,12 +4,7 @@
 #
 # Moritz Scherer <[email protected]>
 
-set(CMAKE_EXPORT_COMPILE_COMMANDS TRUE)
-
-set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib)
-set(CMAKE_LIBRARY_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/lib)
-set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin)
-
 add_subdirectory(generic)
+add_target_source(${TARGET_PLATFORM})
 
 # TODO: Add target-specific test directories

tests/chimera-open/CMakeLists.txt

@@ -0,0 +1,7 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Moritz Scherer <[email protected]>
+
+add_subdirectory(testClusterOffload)

tests/chimera-open/testClusterOffload/CMakeLists.txt

@@ -0,0 +1,18 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Moritz Scherer <[email protected]>
+
+project(chimera-sdk-testClusterOffload LANGUAGES C ASM)
+
+file(GLOB_RECURSE TEST_SRCS
+  "src/testClusterOffload.c"
+)
+
+add_chimera_test(
+  testClusterOffload
+  ${TEST_SRCS}
+)
+
+target_link_libraries(testClusterOffload PUBLIC chimera-sdk)