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FFP: Update LLC to latest version.
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DiyouS committed Aug 31, 2023
1 parent 388e570 commit 89b9c8b
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Showing 9 changed files with 1,633 additions and 1,791 deletions.
10 changes: 5 additions & 5 deletions Bender.lock
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ packages:
- apb
- register_interface
axi:
revision: b08e82534789ab710db4f2bb6b66096dbca361b1
revision: 4fb5a02ef5c96396ac2157bcaf09bb6a05b6a87d
version: null
source:
Git: https://github.com/pulp-platform/axi
Expand All @@ -24,7 +24,7 @@ packages:
- common_verification
- tech_cells_generic
axi_llc:
revision: ce8e00b3a0dce627add3703557ab77e7ad7e5cf5
revision: 75bf70195b86dfb3e7017d68812b87cb06c907b9
version: null
source:
Git: https://github.com/pulp-platform/axi_llc
Expand Down Expand Up @@ -61,8 +61,8 @@ packages:
- common_cells
- register_interface
common_cells:
revision: 0989ff73d0315922791bf42137c0ce0cbb4a76ca
version: 1.30.0
revision: 53b0b58af2db5bd3c850a7038fae170ed78326bb
version: 1.31.1
source:
Git: https://github.com/pulp-platform/common_cells
dependencies:
Expand All @@ -75,7 +75,7 @@ packages:
Git: https://github.com/pulp-platform/common_verification
dependencies: []
cva6:
revision: 8e9d589b5dd264cd98b479f58d0f92a2bf2a7a92
revision: bf806ffa1385876ab70b28df488fafe7ea573a7f
version: null
source:
Git: https://github.com/pulp-platform/cva6
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6 changes: 3 additions & 3 deletions Bender.yml
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Expand Up @@ -13,14 +13,14 @@ package:

dependencies:
apb_uart: { git: "https://github.com/pulp-platform/apb_uart", version: 0.2.1 }
axi: { git: "https://github.com/pulp-platform/axi", rev: b08e825 }
axi_llc: { git: "https://github.com/pulp-platform/axi_llc", rev: ce8e00b }
axi: { git: "https://github.com/pulp-platform/axi", rev: 4fb5a02 }
axi_llc: { git: "https://github.com/pulp-platform/axi_llc", rev: 75bf701 }
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics", version: 0.7.0 }
axi_vga: { git: "https://github.com/pulp-platform/axi_vga", version: 0.1.1 }
clint: { git: "https://github.com/pulp-platform/clint", version: 0.1.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells", version: 1.29.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification", version: 0.2.0 }
cva6: { git: "https://github.com/pulp-platform/cva6", rev: 8e9d589 }
cva6: { git: "https://github.com/pulp-platform/cva6", rev: pulp-v0.3.1 }
iDMA: { git: "https://github.com/pulp-platform/iDMA", rev: 437ffa9 } # TODO: master commit; use next release once out
opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals", version: 0.4.0 }
register_interface: { git: "https://github.com/pulp-platform/register_interface", rev: 50270f7 } # TODO: master commit; use next release once out
Expand Down
4 changes: 2 additions & 2 deletions cheshire.mk
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ REGGEN ?= $(PYTHON3) $(shell $(BENDER) path register_interface)/vendor/lowr
VLOG_ARGS ?= -suppress 2583 -suppress 13314
VSIM ?= vsim

MAXTHREAD ?= 256
MAXPARTITION ?= 16
CACHE_PARTITION ?= 1


Expand Down Expand Up @@ -103,7 +103,7 @@ $(CHS_SLINK_DIR)/.generated: $(CHS_ROOT)/hw/serial_link.hjson

# LLC partitioning configuration
$(CHS_LLC_DIR)/.generated:
$(MAKE) -C $(CHS_LLC_DIR) REGWIDTH=64 CACHENUMLINES=256 MAXTHREAD=$(MAXTHREAD) CACHE_PARTITION=$(CACHE_PARTITION) regs
$(MAKE) -C $(CHS_LLC_DIR) REGWIDTH=64 CACHENUMLINES=256 MAXPARTITION=$(MAXPARTITION) CACHE_PARTITION=$(CACHE_PARTITION) regs
@touch $@

chs-hw-all: $(CHS_ROOT)/hw/regs/cheshire_reg_pkg.sv $(CHS_ROOT)/hw/regs/cheshire_reg_top.sv
Expand Down
1 change: 0 additions & 1 deletion hw/bootrom/cheshire_bootrom.S
Original file line number Diff line number Diff line change
Expand Up @@ -68,7 +68,6 @@ _wait_llc_bist:
sw t1, 84(t0) // partition table configuration
li t1, 1
sw t1, 340(t0) // commit partition configuration
csrwi 0xA00, 4 // write PATID=3'b100 into csr

li t1, -1
sw t1, 0(t0) // llc.CFG_SPM_LOW
Expand Down
3,136 changes: 1,568 additions & 1,568 deletions hw/bootrom/cheshire_bootrom.sv

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10 changes: 6 additions & 4 deletions hw/cheshire_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -130,15 +130,16 @@ package cheshire_pkg;
shrt_bt LlcNumLines;
shrt_bt LlcNumBlocks;
bit LlcCachePartition;
shrt_bt LlcMaxthread;
shrt_bt LlcMaxPartition;
dw_bt LlcMaxReadTxns;
dw_bt LlcMaxWriteTxns;
aw_bt LlcAmoNumCuts;
bit LlcAmoPostCut;
bit LlcOutConnect;
doub_bt LlcOutRegionStart;
doub_bt LlcOutRegionEnd;
dw_bt LlcUserAmoBit;
dw_bt LlcUserAmoMsb;
dw_bt LlcUserAmoLsb;
// Parameters for VGA
byte_bt VgaRedWidth;
byte_bt VgaGreenWidth;
Expand Down Expand Up @@ -467,15 +468,16 @@ package cheshire_pkg;
LlcNumLines : 256,
LlcNumBlocks : 8,
LlcCachePartition : 1,
LlcMaxthread : 256,
LlcMaxPartition : 16,
LlcMaxReadTxns : 8,
LlcMaxWriteTxns : 8,
LlcAmoNumCuts : 1,
LlcAmoPostCut : 1,
LlcOutConnect : 1,
LlcOutRegionStart : 'h8000_0000,
LlcOutRegionEnd : 'h1_0000_0000,
LlcUserAmoBit : 2,
LlcUserAmoMsb : 6,
LlcUserAmoLsb : 2,
// VGA: RGB332
VgaRedWidth : 3,
VgaGreenWidth : 3,
Expand Down
8 changes: 3 additions & 5 deletions hw/cheshire_soc.sv
Original file line number Diff line number Diff line change
Expand Up @@ -477,10 +477,6 @@ module cheshire_soc import cheshire_pkg::*; #(
always_comb begin
axi_llc_remap_req = axi_llc_cut_req;

// Convention: bit 2-9 for LLC
axi_llc_remap_req.aw.user = axi_llc_cut_req.aw.user >> Cfg.LlcUserAmoBit;
axi_llc_remap_req.ar.user = axi_llc_cut_req.ar.user >> Cfg.LlcUserAmoBit;

if (axi_llc_cut_req.aw.addr & ~AmSpmRegionMask == AmSpmBaseUncached & ~AmSpmRegionMask)
axi_llc_remap_req.aw.addr = AmSpm | (AmSpmRegionMask & axi_llc_cut_req.aw.addr);
if (axi_llc_cut_req.ar.addr & ~AmSpmRegionMask == AmSpmBaseUncached & ~AmSpmRegionMask)
Expand All @@ -493,11 +489,13 @@ module cheshire_soc import cheshire_pkg::*; #(
.NumLines ( Cfg.LlcNumLines ),
.NumBlocks ( Cfg.LlcNumBlocks ),
.CachePartition ( Cfg.LlcCachePartition ),
.MaxThread ( Cfg.LlcMaxthread ),
.MaxPartition ( Cfg.LlcMaxPartition ),
.AxiIdWidth ( AxiSlvIdWidth ),
.AxiAddrWidth ( Cfg.AddrWidth ),
.AxiDataWidth ( Cfg.AxiDataWidth ),
.AxiUserWidth ( Cfg.AxiUserWidth ),
.AxiUserIdMsb ( Cfg.LlcUserAmoMsb ),
.AxiUserIdLsb ( Cfg.LlcUserAmoLsb ),
.slv_req_t ( axi_slv_req_t ),
.slv_resp_t ( axi_slv_rsp_t ),
.mst_req_t ( axi_ext_llc_req_t ),
Expand Down
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