Merge pull request #70 from pulp-platform/aottaviano/offload-1

Bare-metal offloading flow - 1

.github/workflows/lint.yml

@@ -29,6 +29,7 @@ jobs:
           sw/include/regs/*.h
           .dir-locals.el
           utils/*
+          scripts/*
 
   lint-sv:
     runs-on: ubuntu-latest

.gitignore

@@ -12,6 +12,7 @@ work/
 /logs/
 /working_dir/
 
+sw/tests/bare-metal/safed/*.h
 
 # Created by https://www.toptal.com/developers/gitignore/api/python
 # Edit at https://www.toptal.com/developers/gitignore?templates=python

Bender.yml

@@ -32,6 +32,9 @@ workspace:
   package_links:
     cheshire: cheshire
     spatz: spatz
+    safety_island: safety_island
+    opentitan: opentitan
+    pulp_cluster: pulp_cluster
 
 sources:
   # Source files grouped in levels. Files in level 0 have no dependencies on files in this
@@ -52,6 +55,7 @@ sources:
   - target: test
     files:
       - tb/hyp_vip/s27ks0641.v
+      - tb/vip_carfield_soc.sv
       - tb/carfield_fix.sv
       - tb/carfield_tb.sv
 
@@ -62,7 +66,7 @@ sources:
   - target: all(synthesis, not(fpga))
     files:
       - target/synth/carfield_synth_wrap.sv
-  
+
   - target: all(xilinx, fpga)
     files:
       - target/xilinx/src/carfield_top_xilinx.sv

CHLG_weekly.md → CHANGELOG_WEEKLY.md

@@ -2,7 +2,33 @@
 
 We keep all RTL changes relevant for weekly releases here
 
-## Weekly 2023_07_12
+## Weekly 2023_07_20 (weekly_20230720)
+
+### Carfield Top
+- Fix out-of-bounds array
+- Add SW test for offloading
+
+### Cheshire
+- Adjust SW build, minor bootrom adjustments
+- Update interrupt routing
+- Update `axi-rt`
+
+### Safety Island
+
+### Security Island
+
+### Spatz
+- Bump spatz to newest version
+  - Add new and fix existing SW tests
+  - Fix undriven nets
+  - Fix race condition between vector store and load
+  - Decouple scatter-gather index width from SEW
+  - Fix hazard detection of indexed memory operations
+  - Propagate testmode signal
+
+### PULP Cluster
+
+## Weekly 2023_07_12 (weekly_20230712)
 
 ### Carfield Top
 * FPGA flow integration
@@ -22,13 +48,15 @@ We keep all RTL changes relevant for weekly releases here
 * Fix atomics
 * Add configurable number of memory banks
 
+### Security Island
+
 ### Spatz
 * Enable custom config now located in carfield repository
 
 ### PULP Cluster
 * Bump unused ibex to fix bender target issue
 
 
-## Weekly 2023_07_06
+## Weekly 2023_07_06 (weekly_20230706)
 
 * Initial tag

README.md

@@ -18,28 +18,33 @@ To handle project dependencies, you can use
 
 ## Carfield Initialization
 To initialize Carfield, do the following:
- * Export the `RISCV` environment variable to the RISC-V toolchain. To work on IIS machines,
- do `export RISCV=/usr/pack/riscv-1.0-kgf/riscv64-gcc-11.2.0`.
- * Execute the command:
+* Execute the command:
 
    ```
    make car-init
    ```
 
    It will take care of:
 
-   ** Clone all the Carfield dependencies;
-   ** Initialize the [Cheshire SoC](https://github.com/pulp-platform/cheshire). This can be
+   1. Clone all the Carfield dependencies;
+   2. Initialize the [Cheshire SoC](https://github.com/pulp-platform/cheshire). This can be
 	  done separately by running `make chs-init`
-   ** Downloads the Hyperram models from the iis-gitlab. If you don't have access to it, you
+   3. Downloads the Hyperram models from the iis-gitlab. If you don't have access to it, you
 	  can also download the freely-available Hyperram models from
 	  [here](https://www.cypress.com/documentation/models/verilog/s27kl0641-s27ks0641-verilog)
 	  and unzip them according to the bender.
 
+* Check that you have a RISCV toolchain for both RV64 and RV32 ISAs. For ETH, type:
+   ```
+   source scripts/env-iis.sh
+   ```
+
 ## Simulation
 
 Follow these steps to launch a Carfield simulation:
 
+### Compile HW and SW
+
 * Generate the compile scripts for Questasim and compile Carfield.
 
    ```
@@ -55,9 +60,11 @@ Follow these steps to launch a Carfield simulation:
   make car-sw-build
   ```
 
-* Simulate a binary in RTL. The current supported bootmodes from Cheshire are:
+### System bootmodes
+
+* The current supported bootmodes from Cheshire are:
 
-  | Bootmode | Preload mode | Action |
+  | `CHS_BOOTMODE` | `CHS_PRELMODE` | Action |
   | --- | --- | --- |
   | 0 | 0 | Passive bootmode, JTAG preload |
   | 0 | 1 | Passive bootmode, Serial Link preload |
@@ -66,18 +73,33 @@ Follow these steps to launch a Carfield simulation:
   | 2 | - | Autonomous bootmode, SPI flash |
   | 3 | - | Autonomous bootmode, I2C EEPROM |
 
-  `Bootmode` indicates the available bootmodes in Cheshire, while `Preload mode`
-  indicates the type of preload, if any is needed. For RTL simulation, bootmodes
-  0, 2 and 3 are supported. SPI SD card bootmode is supported on FPGA emulation.
+  `Bootmode` indicates the available bootmodes in Cheshire, while `Preload mode` indicates the type
+  of preload, if any is needed. For RTL simulation, bootmodes 0, 2 and 3 are supported. SPI SD card
+  bootmode is supported on FPGA emulation.
 
-  To launch an RTL simulation with the selected boot and preload modes, type:
+* The current supported bootmodes ffrom the Safety Island are:
 
-  | Bootmode | Command |
+  | `SAFED_BOOTMODE` | Action |
   | --- | --- |
-  | 0 | `make car-hw-sim BOOTMODE=<bootmode> PRELMODE=<prelmode> CHS_BINARY=<chs_binary_path>.car.elf SECD_BINARY=<secd_binary_path> SAFED_BINARY=<safed_binary_path>`  |
-  | 1, 2, 3 | `make car-hw-sim BOOTMODE=<bootmode> PRELMODE=<prelmode> CHS_IMAGE=<chs_binary_path>.car.memh`  |
+  | 0 | Passive bootmode, JTAG preload |
+  | 1 | Passive bootmode, Serial Link preload |
+
+### Simulation
+
+To launch an RTL simulation with the selected boot/preload modes for the island of choice, type:
+
+
+* For cheshire in passive bootmode (`CHS_BOOTMODE=0`), set `CHS_BINARY` for Cheshire
+
+```
+make car-hw-sim CHS_BOOTMODE=<chs_bootmode> CHS_PRELMODE=<chs_prelmode> CHS_BINARY=<chs_binary_path>.car.elf PULPCL_BINARY=<pulpcl_binary> SPATZCL_BINARY=<spatzcl_binary> SECD_BINARY=<secd_binary_path> SAFED_BOOTMODE=<safed_bootmode> SAFED_BINARY=<safed_binary_path>
+```
+
+* For cheshire in autonomous bootmode (`CHS_BOOTMODE` = {1,2,3}), set `CHS_IMAGE` for Cheshire
 
-  Default is passive bootmode with serial link preload.
+```
+make car-hw-sim CHS_BOOTMODE=<chs_bootmode> CHS_PRELMODE=<chs_prelmode> CHS_IMAGE=<chs_binary_path>.car.memh PULPCL_BINARY=<pulpcl_binary> SPATZCL_BINARY=<spatzcl_binary> SECD_BINARY=<secd_binary_path> SAFED_BOOTMODE=<safed_bootmode> SAFED_BINARY=<safed_binary_path>
+```
 
 ## License
 

bender-common.mk

@@ -1,4 +1,4 @@
-# Copyright 2021 ETH Zurich and University of Bologna.
+# Copyright 2023 ETH Zurich and University of Bologna.
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 #

bender-safed.mk

@@ -0,0 +1,8 @@
+# Copyright 2023 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Author: Alessandro Ottaviano <[email protected]>
+
+# bender defines
+safed_defs += -D TARGET_SIMULATION

bender-synth.mk

@@ -1,4 +1,4 @@
-# Copyright 2021 ETH Zurich and University of Bologna.
+# Copyright 2023 ETH Zurich and University of Bologna.
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 #