fpga: Correcting artifacts mngmt and applied new constraints to genesys2

pulp-platform · Aug 30, 2023 · 5aff4f0 · 5aff4f0
1 parent 468acd9
commit 5aff4f0
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Showing 4 changed files with 31 additions and 17 deletions.
diff --git a/hw/bootrom/cheshire_bootrom.c b/hw/bootrom/cheshire_bootrom.c
@@ -51,7 +51,7 @@ int boot_spi_sdcard(uint64_t core_freq, uint64_t rtc_freq) {
 int boot_spi_s25fs512s(uint64_t core_freq, uint64_t rtc_freq) {
     // Initialize device handle
     spi_s25fs512s_t device = {
-        .spi_freq = MIN(40 * 1000 * 1000, core_freq / 4), // Up to quarter core freq or 40MHz
+        .spi_freq = MIN(40 * 1000 * 1000, core_freq / 5), // Up to quarter core freq or 40MHz
         .csid = 1};
     CHECK_CALL(spi_s25fs512s_init(&device, core_freq))
     // Wait for device to be initialized (t_PU = 300us, round up extra tick to be sure)

diff --git a/target/xilinx/constraints/genesys2.xdc b/target/xilinx/constraints/genesys2.xdc
@@ -7,7 +7,7 @@
 #####################
 
 # 50 MHz SoC clock
-set soc_clk clk_50
+set soc_clk clk_50_xlnx_clk_wiz
 set SOC_TCK 20.0
 
 # I2C High-speed mode is 3.2 Mb/s
@@ -34,20 +34,30 @@ set_clock_groups -name sys_clk_async -asynchronous -group {sys_clk}
 # Mig clock #
 #############
 
-# Dram axi clock : 200MHz
+# Dram axi clock : 200 MHz
 set MIG_TCK 5
-set MIG_RST [get_nets i_dram_wrapper/dram_rst_o]
-create_clock -period $MIG_TCK -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/ui_clk]
-set_clock_groups -name dram_async -asynchronous -group {dram_axi_clk}
-set_false_path -hold -through $MIG_RST
-set_max_delay -through $MIG_RST $MIG_TCK
+create_generated_clock -source [get_pins i_dram_wrapper/i_dram/u_xlnx_mig_7_ddr3_mig/u_ddr3_infrastructure/gen_mmcm.mmcm_i/CLKFBOUT] \
+ -divide_by 1 -add -master_clock clk_pll_i -name dram_axi_clk [get_pins i_dram_wrapper/i_dram/ui_clk]
+# Aynch reset in
+set MIG_RST_I [get_pin i_dram_wrapper/i_dram/aresetn]
+set_false_path -hold -setup -through $MIG_RST_I
+# Synch reset out
+set MIG_RST_O [get_pins i_dram_wrapper/i_dram/ui_clk]
+set_false_path -hold -through $MIG_RST_O
+set_max_delay -through $MIG_RST_O $MIG_TCK
 
 ########
 # CDCs #
 ########
 
-set_max_delay -through [get_nets -of_objects [get_cells i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*] -filter {NAME=~*async*}] $MIG_TCK
-set_max_delay -datapath -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_dst_*/*i_sync/reg*/D] $MIG_TCK
+set_max_delay -datapath \
+ -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \
+  -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*i_sync/reg*/D] $MIG_TCK
+
+set_max_delay -datapath \
+ -from [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/*reg*/C] \
+  -to [get_pins i_dram_wrapper/gen_cdc.i_axi_cdc_mig/i_axi_cdc_*/i_cdc_fifo_gray_*/i_spill_register/spill_register_flushable_i/*reg*/D] $MIG_TCK
+
 
 #######
 # VGA #

diff --git a/target/xilinx/scripts/run.tcl b/target/xilinx/scripts/run.tcl
@@ -2,7 +2,13 @@
 # Solderpad Hardware License, Version 0.51, see LICENSE for details.
 # SPDX-License-Identifier: SHL-0.51
 #
-# Author: Florian Zaruba <[email protected]>
+# Florian Zaruba <[email protected]>
+# Nils Wistoff <[email protected]>
+# Cyril Koenig <[email protected]>
+
+# Ips selection
+set ips $::env(IP_PATHS)
+read_ip $ips
 
 # Contraints files selection
 switch $::env(BOARD) {
@@ -15,10 +21,6 @@ switch $::env(BOARD) {
   }
 }
 
-# Ips selection
-set ips $::env(IP_PATHS)
-read_ip $ips
-
 source scripts/add_sources.tcl
 
 set_property top ${project}_top_xilinx [current_fileset]

diff --git a/target/xilinx/xilinx/common.mk b/target/xilinx/xilinx/common.mk
@@ -37,12 +37,14 @@ generate_sha256:
 load-artifacts: .generated_sha256
 	@if [ -d "$(ARTIFACTS_PATH)/`cat $<`" ]; then\
 		echo "Fetching $(PROJECT) from $(ARTIFACTS_PATH)/`cat $<`"; \
-		cp -r -d $(ARTIFACTS_PATH)/`cat $<`/* .; \
+		cp -r $(ARTIFACTS_PATH)/`cat $<`/* .; \
 	fi
 
 # Save artifacts (this folder) based on .generated_sha256
 save-artifacts: generate_sha256 load-artifacts $(PROJECT).xpr
-	cp -r . $(ARTIFACTS_PATH)/`cat .generated_sha256`/
+	@if [ ! -d "$(ARTIFACTS_PATH)/`cat .generated_sha256`" ]; then \
+		cp -r . $(ARTIFACTS_PATH)/`cat .generated_sha256`; \
+	fi
 
 gui:
 	$(VIVADOENV) $(VIVADO) -mode gui -source tcl/run.tcl &