sw: Add LLC test and bump Cheshire with LLC fix
reviewdog [verible-verilog-lint] report
reported by reviewdog 🐶
Findings (47)
hw/axi_fifo_delay_dyn.sv|49 col 20| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/axi_fifo_delay_dyn.sv|65 col 12| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/axi_fifo_delay_dyn.sv|72 col 20| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/axi_fifo_delay_dyn.sv|88 col 12| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/axi_fifo_delay_dyn.sv|95 col 19| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/axi_fifo_delay_dyn.sv|111 col 12| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/axi_fifo_delay_dyn.sv|118 col 19| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/axi_fifo_delay_dyn.sv|134 col 12| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/axi_fifo_delay_dyn.sv|141 col 19| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/axi_fifo_delay_dyn.sv|157 col 12| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/snitch_cluster_carfield.sv|134 col 101| Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
hw/snitch_cluster_carfield.sv|140 col 101| Line length exceeds max: 100; is: 169 [Style: line-length] [line-length]
hw/snitch_cluster_carfield.sv|141 col 101| Line length exceeds max: 100; is: 169 [Style: line-length] [line-length]
hw/snitch_cluster_carfield.sv|188 col 65| Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
hw/snitch_cluster_carfield.sv|228 col 82| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/snitch_cluster_carfield.sv|453 col 101| Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
hw/snitch_cluster_carfield.sv|493 col 101| Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
hw/snitch_cluster_carfield.sv|503 col 63| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/cheshire_wrap.sv|259 col 101| Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
hw/cheshire_wrap.sv|260 col 101| Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
hw/cheshire_wrap.sv|263 col 11| Explicitly define a storage type for every parameter and localparam, (IOMMU_N_INT_VEC). [Style: constants] [explicit-parameter-storage-type]
hw/cheshire_wrap.sv|470 col 31| All generate block statements must have a label [Style: generate-statements] [generate-label]
hw/cheshire_wrap.sv|497 col 14| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|498 col 14| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|499 col 12| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|500 col 16| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|501 col 14| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|502 col 13| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|503 col 12| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|504 col 12| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|505 col 13| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|506 col 12| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|507 col 13| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|508 col 13| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|509 col 17| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|510 col 17| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|512 col 13| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|513 col 13| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|518 col 16| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|519 col 17| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|524 col 13| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|525 col 12| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|527 col 14| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|528 col 15| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/cheshire_wrap.sv|529 col 16| Use spaces, not tabs. [Style: tabs] [no-tabs]
hw/stream_fifo_delay_dyn.sv|94 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
hw/stream_fifo_delay_dyn.sv|144 col 101| Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
Filtered Findings (0)
Annotations
Check warning on line 49 in hw/axi_fifo_delay_dyn.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/axi_fifo_delay_dyn.sv#L49
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"hw/axi_fifo_delay_dyn.sv" range:{start:{line:49 column:20}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 65 in hw/axi_fifo_delay_dyn.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/axi_fifo_delay_dyn.sv#L65
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"hw/axi_fifo_delay_dyn.sv" range:{start:{line:65 column:12}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 72 in hw/axi_fifo_delay_dyn.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/axi_fifo_delay_dyn.sv#L72
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"hw/axi_fifo_delay_dyn.sv" range:{start:{line:72 column:20}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 88 in hw/axi_fifo_delay_dyn.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/axi_fifo_delay_dyn.sv#L88
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"hw/axi_fifo_delay_dyn.sv" range:{start:{line:88 column:12}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 95 in hw/axi_fifo_delay_dyn.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/axi_fifo_delay_dyn.sv#L95
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"hw/axi_fifo_delay_dyn.sv" range:{start:{line:95 column:19}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 111 in hw/axi_fifo_delay_dyn.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/axi_fifo_delay_dyn.sv#L111
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"hw/axi_fifo_delay_dyn.sv" range:{start:{line:111 column:12}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 118 in hw/axi_fifo_delay_dyn.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/axi_fifo_delay_dyn.sv#L118
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"hw/axi_fifo_delay_dyn.sv" range:{start:{line:118 column:19}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 134 in hw/axi_fifo_delay_dyn.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/axi_fifo_delay_dyn.sv#L134
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"hw/axi_fifo_delay_dyn.sv" range:{start:{line:134 column:12}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 141 in hw/axi_fifo_delay_dyn.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/axi_fifo_delay_dyn.sv#L141
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"hw/axi_fifo_delay_dyn.sv" range:{start:{line:141 column:19}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 157 in hw/axi_fifo_delay_dyn.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/axi_fifo_delay_dyn.sv#L157
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"hw/axi_fifo_delay_dyn.sv" range:{start:{line:157 column:12}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 134 in hw/snitch_cluster_carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster_carfield.sv#L134
Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]" location:{path:"hw/snitch_cluster_carfield.sv" range:{start:{line:134 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 140 in hw/snitch_cluster_carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster_carfield.sv#L140
Line length exceeds max: 100; is: 169 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 169 [Style: line-length] [line-length]" location:{path:"hw/snitch_cluster_carfield.sv" range:{start:{line:140 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 141 in hw/snitch_cluster_carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster_carfield.sv#L141
Line length exceeds max: 100; is: 169 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 169 [Style: line-length] [line-length]" location:{path:"hw/snitch_cluster_carfield.sv" range:{start:{line:141 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 188 in hw/snitch_cluster_carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster_carfield.sv#L188
Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]
Raw output
message:"Remove trailing spaces. [Style: trailing-spaces] [no-trailing-spaces]" location:{path:"hw/snitch_cluster_carfield.sv" range:{start:{line:188 column:65}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"} suggestions:{range:{start:{line:188 column:65} end:{line:189}} text:" NoMstPorts : NrMergeMasters, // Wide out + Narrow out\n"}
Check warning on line 228 in hw/snitch_cluster_carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster_carfield.sv#L228
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"hw/snitch_cluster_carfield.sv" range:{start:{line:228 column:82}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 453 in hw/snitch_cluster_carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster_carfield.sv#L453
Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 123 [Style: line-length] [line-length]" location:{path:"hw/snitch_cluster_carfield.sv" range:{start:{line:453 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 493 in hw/snitch_cluster_carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster_carfield.sv#L493
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]" location:{path:"hw/snitch_cluster_carfield.sv" range:{start:{line:493 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 503 in hw/snitch_cluster_carfield.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/snitch_cluster_carfield.sv#L503
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"hw/snitch_cluster_carfield.sv" range:{start:{line:503 column:63}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 259 in hw/cheshire_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_wrap.sv#L259
Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]" location:{path:"hw/cheshire_wrap.sv" range:{start:{line:259 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 260 in hw/cheshire_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_wrap.sv#L260
Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
Raw output
message:"Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]" location:{path:"hw/cheshire_wrap.sv" range:{start:{line:260 column:101}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 263 in hw/cheshire_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_wrap.sv#L263
Explicitly define a storage type for every parameter and localparam, (IOMMU_N_INT_VEC). [Style: constants] [explicit-parameter-storage-type]
Raw output
message:"Explicitly define a storage type for every parameter and localparam, (IOMMU_N_INT_VEC). [Style: constants] [explicit-parameter-storage-type]" location:{path:"hw/cheshire_wrap.sv" range:{start:{line:263 column:11}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 470 in hw/cheshire_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_wrap.sv#L470
All generate block statements must have a label [Style: generate-statements] [generate-label]
Raw output
message:"All generate block statements must have a label [Style: generate-statements] [generate-label]" location:{path:"hw/cheshire_wrap.sv" range:{start:{line:470 column:31}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 497 in hw/cheshire_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_wrap.sv#L497
Use spaces, not tabs. [Style: tabs] [no-tabs]
Raw output
message:"Use spaces, not tabs. [Style: tabs] [no-tabs]" location:{path:"hw/cheshire_wrap.sv" range:{start:{line:497 column:14}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 498 in hw/cheshire_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_wrap.sv#L498
Use spaces, not tabs. [Style: tabs] [no-tabs]
Raw output
message:"Use spaces, not tabs. [Style: tabs] [no-tabs]" location:{path:"hw/cheshire_wrap.sv" range:{start:{line:498 column:14}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}
Check warning on line 499 in hw/cheshire_wrap.sv
github-actions / verible-verilog-lint
[verible-verilog-lint] hw/cheshire_wrap.sv#L499
Use spaces, not tabs. [Style: tabs] [no-tabs]
Raw output
message:"Use spaces, not tabs. [Style: tabs] [no-tabs]" location:{path:"hw/cheshire_wrap.sv" range:{start:{line:499 column:12}}} severity:WARNING source:{name:"verible-verilog-lint" url:"https://github.com/chipsalliance/verible"}