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fpga: Testing hyperram in block design
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@CyrilKoe
CyrilKoe committed Jun 14, 2024
1 parent cb357a4 commit 60b0af1
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Showing 6 changed files with 34 additions and 20 deletions.
2 changes: 1 addition & 1 deletion carfield.mk
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Expand Up @@ -44,7 +44,7 @@ include $(CAR_ROOT)/bender-safed.mk
######################

CAR_NONFREE_REMOTE ?= [email protected]:carfield/carfield-nonfree.git
CAR_NONFREE_COMMIT ?= 59e53134
CAR_NONFREE_COMMIT ?= 42de7659

## @section Carfield platform nonfree components
## Clone the non-free verification IP for Carfield. Some components such as CI scripts and ASIC
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15 changes: 9 additions & 6 deletions target/xilinx/flavor_bd/.gitignore
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@@ -1,6 +1,9 @@
.Xil
carfield_*
scripts/add_sources.tcl*
scripts/add_includes.tcl
out/
probes.ltx
# Makefile
/out/
# Bender
/scripts/add_sources.tcl*
/scripts/add_includes.tcl
# Vivado
/.Xil
/carfield_*
/probes.ltx
12 changes: 6 additions & 6 deletions target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc
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Expand Up @@ -14,8 +14,8 @@ set_property PACKAGE_PIN A24 [get_ports "pad_hyper_csn[1]"] ;# (FMCP
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA13_N) Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72
set_property PACKAGE_PIN A25 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA13_P) Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA13_P) Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72
set_property PACKAGE_PIN C23 [get_ports "pad_hyper_rwds[0]"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_rwds[0]"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72
set_property PACKAGE_PIN C23 [get_ports "pad_hyper_rwds"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_rwds"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72
set_property PACKAGE_PIN D26 [get_ports "pad_hyper_dq[2] "] ;# (FMCP_HSPC_LA09_N) Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[2] "] ;# (FMCP_HSPC_LA09_N) Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72
set_property PACKAGE_PIN A23 [get_ports pad_hyper_dq[3]] ;# (FMCP_HSPC_LA10_N)
Expand All @@ -28,10 +28,10 @@ set_property PACKAGE_PIN D22 [get_ports "pad_hyper_dq[7]"] ;# (FMCP_HSPC_LA
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[7]"] ;# (FMCP_HSPC_LA06_N) Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72
set_property PACKAGE_PIN E22 [get_ports "pad_hyper_dq[1]"] ;# (FMCP_HSPC_LA06_P) Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[1]"] ;# (FMCP_HSPC_LA06_P) Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72
set_property PACKAGE_PIN F25 [get_ports "pad_hyper_ckn[0]"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ckn[0]"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72
set_property PACKAGE_PIN F26 [get_ports "pad_hyper_ck[0]"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ck[0]"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72
set_property PACKAGE_PIN F25 [get_ports "pad_hyper_ckn"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ckn"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72
set_property PACKAGE_PIN F26 [get_ports "pad_hyper_ck"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ck"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72
set_property PACKAGE_PIN G27 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA05_N) Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72
set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA05_N) Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72
set_property PACKAGE_PIN H27 [get_ports "pad_hyper_dq[6]"] ;# (FMCP_HSPC_LA05_P) Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72
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17 changes: 17 additions & 0 deletions target/xilinx/flavor_bd/scripts/carfield_bd_hyperbus.tcl
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@@ -0,0 +1,17 @@
# Copyright 2020 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
#
# Cyril Koenig <[email protected]>

set pad_hyper_ck [ create_bd_port -dir IO pad_hyper_ck ]
set pad_hyper_ckn [ create_bd_port -dir IO pad_hyper_ckn ]
set pad_hyper_csn [ create_bd_port -dir IO -from 1 -to 0 pad_hyper_csn ]
set pad_hyper_dq [ create_bd_port -dir IO -from 7 -to 0 pad_hyper_dq ]
set pad_hyper_rwds [ create_bd_port -dir IO pad_hyper_rwds ]

connect_bd_net [get_bd_ports pad_hyper_csn] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_csn]
connect_bd_net [get_bd_ports pad_hyper_ck] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ck]
connect_bd_net [get_bd_ports pad_hyper_ckn] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ckn]
connect_bd_net [get_bd_ports pad_hyper_rwds] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_rwds]
connect_bd_net [get_bd_ports pad_hyper_dq] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_dq]
5 changes: 0 additions & 5 deletions target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl
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Expand Up @@ -463,11 +463,6 @@ proc create_root_design { parentCell } {
connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x1] [get_bd_intf_pins xdma_0/pcie_mgt]

# Create port connections
connect_bd_net -net Net [get_bd_pins carfield_xilinx_ip_0/pad_hyper_csn]
connect_bd_net -net Net1 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ck]
connect_bd_net -net Net2 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ckn]
connect_bd_net -net Net3 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_rwds]
connect_bd_net -net Net4 [get_bd_pins carfield_xilinx_ip_0/pad_hyper_dq]
connect_bd_net -net axi_dma_0_mm2s_cntrl_reset_out_n [get_bd_pins axi_dma_0/mm2s_cntrl_reset_out_n] [get_bd_pins axi_ethernet_0/axi_txc_arstn]
connect_bd_net -net axi_dma_0_mm2s_introut [get_bd_pins axi_dma_0/mm2s_introut] [get_bd_pins concat_irq/In2]
connect_bd_net -net axi_dma_0_mm2s_prmry_reset_out_n [get_bd_pins axi_dma_0/mm2s_prmry_reset_out_n] [get_bd_pins axi_ethernet_0/axi_txd_arstn]
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3 changes: 1 addition & 2 deletions target/xilinx/flavor_bd/scripts/run.tcl
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Expand Up @@ -34,9 +34,8 @@ if {[info exists ::env(GEN_EXT_JTAG)] && ($::env(GEN_EXT_JTAG)==1)} {

# Add the hyperbus pins to block design
if {![info exists ::env(GEN_NO_HYPERBUS)] || ($::env(GEN_NO_HYPERBUS)==0)} {
source scripts/carfield_bd_hyperbus.tcl
import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD)_hyperbus.xdc
} else {
delete_bd_objs [get_bd_ports pad_hyper*]
}

make_wrapper -files [get_files $project/$project.srcs/sources_1/bd/design_1/design_1.bd] -top
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