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[hardware] WIP Vrgather vcompress
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@mp-17
mp-17 committed Nov 27, 2024
1 parent 5b67514 commit 4cc5492
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Showing 6 changed files with 103 additions and 38 deletions.
12 changes: 8 additions & 4 deletions hardware/src/ara_dispatcher.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -625,16 +625,15 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
6'b001011: ara_req.op = ara_pkg::VXOR;
6'b001100: begin
ara_req.op = ara_pkg::VRGATHER;
ara_req.eew_vs1 = eew_q[ara_req.vs1];
ara_req.eew_vs2 = eew_q[ara_req.vs1];
// The MASKU will ask for elements from vs2 through the MaskB opqueue
// and deshuffle them with eew_vd_op encoding
ara_req.eew_vd_op = eew_q[ara_req.vs2];
end
6'b001110: begin // VRGATHEREI16
ara_req.op = ara_pkg::VRGATHEREI16;
// This allows the MASKU to deshuffle vs1 correctly
// Then, the MASKU will treat vs1 with eew == EW16
ara_req.eew_vs1 = eew_q[ara_req.vs1];
// This allows the MASKU to deshuffle vs1 correctly since it gets deshuffled with eew_vs2
ara_req.eew_vs2 = eew_q[ara_req.vs1];
// The MASKU will ask for elements from vs2 through the MaskB opqueue
// and deshuffle them with eew_vd_op encoding
ara_req.eew_vd_op = eew_q[ara_req.vs2];
Expand Down Expand Up @@ -1490,6 +1489,11 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
6'b001011: ara_req.op = ara_pkg::VASUB;
6'b010111: begin
ara_req.op = ara_pkg::VCOMPRESS;
// Correctly deshuffle vs1 (it gets deshuffled with eew_vs2)
ara_req.eew_vs2 = eew_q[ara_req.vs1];
// The MASKU will ask for elements from vs2 through the MaskB opqueue
// and deshuffle them with eew_vd_op encoding
ara_req.eew_vd_op = eew_q[ara_req.vs2];
// Encoding corresponding to unmasked operations are reserved
if (!insn.varith_type.vm) illegal_insn = 1'b1;
end
Expand Down
2 changes: 1 addition & 1 deletion hardware/src/lane/lane.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -442,7 +442,7 @@ module lane import ara_pkg::*; import rvv_pkg::*; #(
.operand_queue_cmd_i (operand_queue_cmd ),
.operand_queue_cmd_valid_i (operand_queue_cmd_valid ),
// Interface with the Lane Sequencer
.mask_b_cmd_pop_o (mask_b_cmd_pop ),
.mask_b_cmd_pop_o (mask_b_cmd_pop ),
// Interface with the VFUs
// ALU
.alu_operand_o (alu_operand ),
Expand Down
23 changes: 20 additions & 3 deletions hardware/src/lane/lane_sequencer.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -315,7 +315,8 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
vm : pe_req.vm,
vfu : pe_req.vfu,
use_vs1 : pe_req.use_vs1,
use_vs2 : pe_req.use_vs2,
// vrgather/vcompress request vs2 in a non-conventional way from MaskB, not ALU
use_vs2 : pe_req.use_vs2 && !(pe_req.op inside {[VRGATHER:VCOMPRESS]}),
use_vd_op : pe_req.use_vd_op,
scalar_op : pe_req.scalar_op,
use_scalar_op : pe_req.use_scalar_op,
Expand Down Expand Up @@ -410,6 +411,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
eew : EW64,
vtype : pe_req.vtype,
vl : pe_req.vl / NrLanes / ELEN,
cvt_resize : pe_req.cvt_resize,
vstart : vfu_operation_d.vstart,
hazard : pe_req.hazard_vm | pe_req.hazard_vd,
default: '0
Expand Down Expand Up @@ -493,6 +495,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
eew : EW64,
vtype : pe_req.vtype,
vl : pe_req.vl / NrLanes / ELEN,
cvt_resize : pe_req.cvt_resize,
vstart : vfu_operation_d.vstart,
hazard : pe_req.hazard_vm | pe_req.hazard_vd,
default: '0
Expand All @@ -511,6 +514,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
eew : EW64,
vtype : pe_req.vtype,
vl : pe_req.vl / NrLanes / ELEN,
cvt_resize : pe_req.cvt_resize,
vstart : vfu_operation_d.vstart,
hazard : pe_req.hazard_vm | pe_req.hazard_vd,
default: '0
Expand All @@ -530,6 +534,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
target_fu: MFPU_ADDRGEN,
vl : pe_req_i.vl / NrLanes,
scale_vl : pe_req_i.scale_vl,
cvt_resize : pe_req.cvt_resize,
vstart : vfu_operation_d.vstart,
vtype : pe_req_i.vtype,
hazard : pe_req_i.hazard_vs2 | pe_req_i.hazard_vd,
Expand All @@ -550,6 +555,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
eew : pe_req.old_eew_vs1,
conv : pe_req.conversion_vs1,
scale_vl: pe_req.scale_vl,
cvt_resize : pe_req.cvt_resize,
vtype : pe_req.vtype,
vl : vfu_operation_d.vl,
vstart : vfu_operation_d.vstart,
Expand All @@ -571,6 +577,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
eew : EW64,
vtype : pe_req.vtype,
vl : pe_req.vl / NrLanes / ELEN,
cvt_resize : pe_req.cvt_resize,
vstart : vfu_operation_d.vstart,
hazard : pe_req.hazard_vm | pe_req.hazard_vd,
default: '0
Expand All @@ -591,6 +598,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
target_fu: MFPU_ADDRGEN,
vl : pe_req_i.vl / NrLanes,
scale_vl : pe_req_i.scale_vl,
cvt_resize : pe_req.cvt_resize,
vstart : vfu_operation_d.vstart,
vtype : pe_req_i.vtype,
hazard : pe_req_i.hazard_vs2 | pe_req_i.hazard_vd,
Expand All @@ -612,6 +620,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
target_fu: ALU_SLDU,
is_slide : 1'b1,
scale_vl : pe_req.scale_vl,
cvt_resize : pe_req.cvt_resize,
vtype : pe_req.vtype,
vstart : vfu_operation_d.vstart,
hazard : pe_req.hazard_vs2 | pe_req.hazard_vd,
Expand Down Expand Up @@ -671,6 +680,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
vs : VMASK,
eew : EW64,
is_slide: 1'b1,
cvt_resize : pe_req.cvt_resize,
vtype : pe_req.vtype,
vstart : vfu_operation_d.vstart,
hazard : pe_req.hazard_vm | pe_req.hazard_vd,
Expand Down Expand Up @@ -712,6 +722,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
id : pe_req.id,
vs : pe_req.vs1,
scale_vl: pe_req.scale_vl,
cvt_resize : pe_req.cvt_resize,
vtype : pe_req.vtype,
vstart : vfu_operation_d.vstart,
hazard : pe_req.hazard_vs1 | pe_req.hazard_vd,
Expand All @@ -723,7 +734,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
// Integer comparisons run on the ALU and then get reshuffled and masked in the MASKU
if (pe_req.op inside {[VMSEQ:VMSBC],[VRGATHER:VRGATHEREI16]}) begin
// These source regs contain non-mask vectors.
operand_request[AluA].eew = pe_req.eew_vs1;
operand_request[AluA].eew = pe_req.op == VRGATHEREI16 ? EW16 : pe_req.vtype.vsew;
operand_request[AluA].vl = pe_req.vl / NrLanes;
if ((operand_request[AluA].vl * NrLanes) != pe_req.vl)
operand_request[AluA].vl += 1;
Expand All @@ -742,6 +753,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
vs : pe_req.vs2,
eew : pe_req.eew_vs2,
scale_vl: pe_req.scale_vl,
cvt_resize : pe_req.cvt_resize,
vtype : pe_req.vtype,
vstart : vfu_operation_d.vstart,
hazard : pe_req.hazard_vs2 | pe_req.hazard_vd,
Expand All @@ -764,14 +776,15 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
if (operand_request[AluB].vl * NrLanes * ELEN != pe_req.vl)
operand_request[AluB].vl += 1;
end
operand_request_push[AluB] = pe_req.use_vs2 && !(pe_req.op inside {[VMFEQ:VMFGE], [VRGATHER:VCOMPRESS]});
operand_request_push[AluB] = pe_req.use_vs2 && !(pe_req.op inside {[VMFEQ:VMFGE],[VRGATHER:VCOMPRESS]});

// Mask fp comparisons
operand_request[MulFPUA] = '{
id : pe_req.id,
vs : pe_req.vs1,
eew : pe_req.eew_vs1,
scale_vl: pe_req.scale_vl,
cvt_resize : pe_req.cvt_resize,
vl : pe_req.vl / NrLanes,
vtype : pe_req.vtype,
vstart : vfu_operation_d.vstart,
Expand All @@ -793,6 +806,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
vs : pe_req.vs2,
eew : pe_req.eew_vs2,
scale_vl: pe_req.scale_vl,
cvt_resize : pe_req.cvt_resize,
vl : pe_req.vl / NrLanes,
vtype : pe_req.vtype,
vstart : vfu_operation_d.vstart,
Expand All @@ -814,6 +828,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
id : pe_req.id,
vs : pe_req.vd,
scale_vl: pe_req.scale_vl,
cvt_resize : pe_req.cvt_resize,
vtype : pe_req.vtype,
vstart : vfu_operation_d.vstart,
hazard : pe_req.hazard_vd,
Expand Down Expand Up @@ -848,6 +863,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
vs : VMASK,
eew : EW64,
vtype : pe_req.vtype,
cvt_resize : pe_req.cvt_resize,
vl : (pe_req.vl / NrLanes / ELEN),
vstart : vfu_operation_d.vstart,
hazard : pe_req.hazard_vm,
Expand Down Expand Up @@ -887,6 +903,7 @@ module lane_sequencer import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::
vs : masku_vrgat_req_q.vs,
eew : masku_vrgat_req_q.eew,
scale_vl : 1'b0,
cvt_resize : pe_req.cvt_resize,
vl : 1,
vstart : masku_vrgat_req_q.idx,
hazard : '0,
Expand Down
2 changes: 0 additions & 2 deletions hardware/src/lane/operand_requester.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -39,8 +39,6 @@ module operand_requester import ara_pkg::*; import rvv_pkg::*; #(
output logic [NrOperandQueues-1:0] operand_issued_o,
output operand_queue_cmd_t [NrOperandQueues-1:0] operand_queue_cmd_o,
output logic [NrOperandQueues-1:0] operand_queue_cmd_valid_o,
// VRGATHER/VCOMPRESS support
output logic masku_b_operand_queue_ready_o,
// Interface with the VFUs
// ALU
input logic alu_result_req_i,
Expand Down
7 changes: 5 additions & 2 deletions hardware/src/lane/valu.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -400,6 +400,7 @@ module valu import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width;

// How many elements are issued/committed
logic [3:0] element_cnt_buf_issue, element_cnt_buf_commit;
logic [1:0] issue_effective_eew, commit_effective_eew;
logic [6:0] element_cnt_issue;
logic [6:0] element_cnt_commit;

Expand Down Expand Up @@ -445,10 +446,12 @@ module valu import ara_pkg::*; import rvv_pkg::*; import cf_math_pkg::idx_width;
prevent_commit = 1'b0;

// How many elements are we processing this cycle?
element_cnt_buf_issue = 1 << (unsigned'(EW64) - unsigned'(vinsn_issue_q.vtype.vsew));
issue_effective_eew = vinsn_issue_q.op == VRGATHEREI16 ? 1 : unsigned'(vinsn_issue_q.vtype.vsew[1:0]);
element_cnt_buf_issue = 1 << (unsigned'(EW64) - issue_effective_eew);
element_cnt_issue = vinsn_issue_q.op inside {[VMSBF:VMXNOR]} ? ELEN : {2'b0, element_cnt_buf_issue};

element_cnt_buf_commit = 1 << (unsigned'(EW64) - unsigned'(vinsn_commit.vtype.vsew));
commit_effective_eew = vinsn_commit.op == VRGATHEREI16 ? 1 : unsigned'(vinsn_commit.vtype.vsew[1:0]);
element_cnt_buf_commit = 1 << (unsigned'(EW64) - commit_effective_eew);
element_cnt_commit = vinsn_commit.op inside {[VMSBF:VMXNOR]} ? ELEN : {2'b0, element_cnt_buf_commit};

////////////////////////////////////////
Expand Down
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