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[RV64_DYNAREC] Added C1 /7 SAR opcode #559

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merged 1 commit into from
Mar 14, 2023
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xctan
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@xctan xctan commented Mar 14, 2023

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@ksco
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ksco commented Mar 14, 2023

I'm not sure, but is there any chance we can simply clear out some flags? e.g. c >= rex.w ? 64 : 32?

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ksco commented Mar 14, 2023

Oh it's a shift right arithmetic, then we need to peek at MSB also, but it might result in fewer RISC-V instructions.

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xctan commented Mar 14, 2023

Still work in progress, currently 32-bit version is not implemented, and some flags can be optimized.

@xctan xctan marked this pull request as draft March 14, 2023 02:54
@xctan xctan force-pushed the rv64_dynarec_c1_7 branch 2 times, most recently from b5d6233 to 20bf5ea Compare March 14, 2023 07:09
@xctan xctan marked this pull request as ready for review March 14, 2023 07:20
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ptitSeb commented Mar 14, 2023

There is a branch conflict now, sorry. Can you fix it @xctan ?

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xctan commented Mar 14, 2023

Sure.

@ptitSeb ptitSeb merged commit c48a225 into ptitSeb:main Mar 14, 2023
fengjixuchui added a commit to fengjixuchui/box64 that referenced this pull request Mar 14, 2023
[RV64_DYNAREC] Added C1 /7 SAR opcode (ptitSeb#559)
@xctan xctan deleted the rv64_dynarec_c1_7 branch March 21, 2023 02:21
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3 participants