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[COSIM] Fix x87 testing #1029

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Oct 15, 2023
Merged

[COSIM] Fix x87 testing #1029

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23 changes: 11 additions & 12 deletions src/dynarec/arm64/dynarec_arm64_functions.c
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Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,6 @@
#define XMM8 16
#define X870 8
#define EMM0 8
#define SCRATCH0 24

// Get a FPU scratch reg
int fpu_get_scratch(dynarec_arm_t* dyn)
Expand Down Expand Up @@ -139,7 +138,7 @@ int neoncache_get_st_f(dynarec_arm_t* dyn, int ninst, int a)
&& dyn->insts[ninst].n.neoncache[i].n==a)
return i;
return -1;
}
}
int neoncache_get_st_f_i64(dynarec_arm_t* dyn, int ninst, int a)
{
/*if(a+dyn->insts[ninst].n.stack_next-st<0)
Expand All @@ -150,47 +149,47 @@ int neoncache_get_st_f_i64(dynarec_arm_t* dyn, int ninst, int a)
&& dyn->insts[ninst].n.neoncache[i].n==a)
return i;
return -1;
}
}
int neoncache_get_st_f_noback(dynarec_arm_t* dyn, int ninst, int a)
{
for(int i=0; i<24; ++i)
if(dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F
&& dyn->insts[ninst].n.neoncache[i].n==a)
return i;
return -1;
}
}
int neoncache_get_st_f_i64_noback(dynarec_arm_t* dyn, int ninst, int a)
{
for(int i=0; i<24; ++i)
if((dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_I64 || dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F)
&& dyn->insts[ninst].n.neoncache[i].n==a)
return i;
return -1;
}
}
int neoncache_get_current_st_f(dynarec_arm_t* dyn, int a)
{
for(int i=0; i<24; ++i)
if(dyn->n.neoncache[i].t==NEON_CACHE_ST_F
&& dyn->n.neoncache[i].n==a)
return i;
return -1;
}
}
int neoncache_get_current_st_f_i64(dynarec_arm_t* dyn, int a)
{
for(int i=0; i<24; ++i)
if((dyn->n.neoncache[i].t==NEON_CACHE_ST_I64 || dyn->n.neoncache[i].t==NEON_CACHE_ST_F)
&& dyn->n.neoncache[i].n==a)
return i;
return -1;
}
}
static void neoncache_promote_double_forward(dynarec_arm_t* dyn, int ninst, int maxinst, int a);
static void neoncache_promote_double_internal(dynarec_arm_t* dyn, int ninst, int maxinst, int a);
static void neoncache_promote_double_combined(dynarec_arm_t* dyn, int ninst, int maxinst, int a)
{
if(a == dyn->insts[ninst].n.combined1 || a == dyn->insts[ninst].n.combined2) {
if(a == dyn->insts[ninst].n.combined1) {
a = dyn->insts[ninst].n.combined2;
} else
} else
a = dyn->insts[ninst].n.combined1;
int i = neoncache_get_st_f_i64_noback(dyn, ninst, a);
//if(box64_dynarec_dump) dynarec_log(LOG_NONE, "neoncache_promote_double_combined, ninst=%d combined%c %d i=%d (stack:%d/%d)\n", ninst, (a == dyn->insts[ninst].n.combined2)?'2':'1', a ,i, dyn->insts[ninst].n.stack_push, -dyn->insts[ninst].n.stack_pop);
Expand Down Expand Up @@ -314,7 +313,7 @@ static int isCacheEmpty(dynarec_native_t* dyn, int ninst) {
for(int i=0; i<24; ++i)
if(dyn->insts[ninst].n.neoncache[i].v) { // there is something at ninst for i
if(!(
(dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F
(dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F
|| dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_D
|| dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_I64)
&& dyn->insts[ninst].n.neoncache[i].n<dyn->insts[ninst].n.stack_pop))
Expand All @@ -339,7 +338,7 @@ int fpuCacheNeedsTransform(dynarec_arm_t* dyn, int ninst) {
for(int i=0; i<24 && !ret; ++i)
if(dyn->insts[ninst].n.neoncache[i].v) { // there is something at ninst for i
if(!(
(dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F
(dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_F
|| dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_D
|| dyn->insts[ninst].n.neoncache[i].t==NEON_CACHE_ST_I64)
&& dyn->insts[ninst].n.neoncache[i].n<dyn->insts[ninst].n.stack_pop))
Expand Down Expand Up @@ -377,7 +376,7 @@ void neoncacheUnwind(neoncache_t* cache)
{
if(cache->swapped) {
// unswap
int a = -1;
int a = -1;
int b = -1;
for(int j=0; j<24 && ((a==-1) || (b==-1)); ++j)
if((cache->neoncache[j].t == NEON_CACHE_ST_D || cache->neoncache[j].t == NEON_CACHE_ST_F || cache->neoncache[j].t == NEON_CACHE_ST_I64)) {
Expand Down Expand Up @@ -580,4 +579,4 @@ void inst_name_pass3(dynarec_native_t* dyn, int ninst, const char* name, rex_t r
void print_opcode(dynarec_native_t* dyn, int ninst, uint32_t opcode)
{
dynarec_log(LOG_NONE, "\t%08x\t%s\n", opcode, arm64_print(opcode, (uintptr_t)dyn->block));
}
}
2 changes: 2 additions & 0 deletions src/dynarec/arm64/dynarec_arm64_functions.h
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Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,8 @@

#include "../dynarec_native_functions.h"

#define SCRATCH0 24

// Get an FPU scratch reg
int fpu_get_scratch(dynarec_arm_t* dyn);
// Reset scratch regs counter
Expand Down
6 changes: 5 additions & 1 deletion src/dynarec/arm64/dynarec_arm64_helper.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1110,7 +1110,11 @@ static void x87_reflectcache(dynarec_arm_t* dyn, int ninst, int s1, int s2, int
if(dyn->n.x87cache[i]!=-1) {
ADDw_U12(s3, s2, dyn->n.x87cache[i]);
ANDw_mask(s3, s3, 0, 2); // mask=7 // (emu->top + i)&7
VSTR64_REG_LSL3(dyn->n.x87reg[i], s1, s3);
if(neoncache_get_st_f(dyn, ninst, dyn->n.x87cache[i])>=0) {
FCVT_D_S(SCRATCH0, dyn->n.x87reg[i]);
VSTR64_REG_LSL3(SCRATCH0, s1, s3);
} else
VSTR64_REG_LSL3(dyn->n.x87reg[i], s1, s3);
}
}

Expand Down