CI: Skip cache segment download after 3 minutes

[arkq]

Problem

GitHub cache action is not stable enough in our setup.... Probably because of cache blob size which is ~1.5GB and lots of jobs spawned at the same time.
One can subscribe to this issues actions/cache#1141 for monitoring the status.

Changes

Set non-fatal timeout for cache blob download to 3 minutes. After that time the cache action will be skipped and the rest of the workflow will continue to run.
https://github.com/actions/cache/blob/main/tips-and-workarounds.md#cache-segment-restore-timeout

[github-actions]

PR #26500: Size comparison from bb3ce44 to f468151

Increases (1 build for cc32xx)

platform	target	config	section	bb3ce44	f468151	change	% change
cc32xx	lock	CC3235SF_LAUNCHXL	.debug_info	19674626	19674628	2	0.0

Full report (1 build for cc32xx)

platform	target	config	section	bb3ce44	f468151	change	% change
cc32xx	lock	CC3235SF_LAUNCHXL		0	0	0	0.0
			(read only)	605002	605002	0	0.0
			(read/write)	204164	204164	0	0.0
			.ARM.attributes	44	44	0	0.0
			.ARM.exidx	8	8	0	0.0
			.bss	197576	197576	0	0.0
			.comment	206	206	0	0.0
			.data	1468	1468	0	0.0
			.debug_abbrev	957619	957619	0	0.0
			.debug_aranges	101232	101232	0	0.0
			.debug_frame	342080	342080	0	0.0
			.debug_info	19674626	19674628	2	0.0
			.debug_line	2671903	2671903	0	0.0
			.debug_line_str	513	513	0	0.0
			.debug_loc	33340	33340	0	0.0
			.debug_loclists	1491139	1491139	0	0.0
			.debug_ranges	4984	4984	0	0.0
			.debug_rnglists	94412	94412	0	0.0
			.debug_str	3131828	3131828	0	0.0
			.ramVecs	780	780	0	0.0
			.resetVecs	64	64	0	0.0
			.rodata	104314	104314	0	0.0
			.shstrtab	265	265	0	0.0
			.stack	2048	2048	0	0.0
			.strtab	483089	483089	0	0.0
			.symtab	287232	287232	0	0.0
			.text	498564	498564	0	0.0

[github-actions]

PR #26500: Size comparison from bb3ce44 to dc82589

Increases (1 build for cc32xx)

platform	target	config	section	bb3ce44	dc82589	change	% change
cc32xx	lock	CC3235SF_LAUNCHXL	.debug_info	19674626	19674628	2	0.0

Full report (1 build for cc32xx)

platform	target	config	section	bb3ce44	dc82589	change	% change
cc32xx	lock	CC3235SF_LAUNCHXL		0	0	0	0.0
			(read only)	605002	605002	0	0.0
			(read/write)	204164	204164	0	0.0
			.ARM.attributes	44	44	0	0.0
			.ARM.exidx	8	8	0	0.0
			.bss	197576	197576	0	0.0
			.comment	206	206	0	0.0
			.data	1468	1468	0	0.0
			.debug_abbrev	957619	957619	0	0.0
			.debug_aranges	101232	101232	0	0.0
			.debug_frame	342080	342080	0	0.0
			.debug_info	19674626	19674628	2	0.0
			.debug_line	2671903	2671903	0	0.0
			.debug_line_str	513	513	0	0.0
			.debug_loc	33340	33340	0	0.0
			.debug_loclists	1491139	1491139	0	0.0
			.debug_ranges	4984	4984	0	0.0
			.debug_rnglists	94412	94412	0	0.0
			.debug_str	3131828	3131828	0	0.0
			.ramVecs	780	780	0	0.0
			.resetVecs	64	64	0	0.0
			.rodata	104314	104314	0	0.0
			.shstrtab	265	265	0	0.0
			.stack	2048	2048	0	0.0
			.strtab	483089	483089	0	0.0
			.symtab	287232	287232	0	0.0
			.text	498564	498564	0	0.0